DFT version

RTL Synthesis using Design Compiler

Learning Outcomes:

After completing this unit, you should be able to:

  1. Set up the DC RTL Synthesis Software and run synthesis tasks
  2. Synthesize a simple RTL design
  3. Create your own scripts
  4. Carry out basic timing and power analysis based on the results

Digital Design Flow

Design Compiler Lab Instructions

For this lab you will need:

  1. A synthesizable Verilog of the design (this is provided)
  2. Library Setup File (this is provided)

Synthesis Process

Set up the library
Read in Design
Elaborate
Add Constraints
Map
Design Analysis
Timing Optimization
Design Write Out

Design Directory Management

  1. Create a directory for your digital design project (e.g. ~/design/ams/ams_demo)
  2. Inside this directory create sub-directories called behavioural, constraints and gate_level. Copy your hdl design files into the behavioural directory.
  3. Also create a sub-directory for your synthesis files and call it synthesis. You need to save the library setup file ".synopsys_dc.setup" in this folder.
    note that you will probably have to rename this file as it is likely to have been saved without the first "."
    (alternatively if you run the command do_c35b4_copy_synopsys_setup from within the synthesis directory this should copy the setup file and give it the correct name). 
                               ams_demo
          ________________________|______________________
         |               |               |               |
    behavioural      constraints     gate_level      synthesis

How to setup Linux Environment to run DC

Read in the HDL

Elaboration

Add Constraints

Add Constraints: Defining the clock

Add Constraints: Optimize Area

Synthesis

Design For Test

To improve the testability of the fabricated chips (so we can quickly discard those with fabrication faults), we can get the tools to add Design For Test (DFT) structures to the existing design.

Using the procedure below, we can add a single scan path to our design. Although there are many more sophisticated DFT structures that we could consider, a single scan path is conceptually very simple and should be enough for most student designs.

Design Analysis

Design Analysis: Power Report

Design Analysis: Timing

Design Analysis: Save Reports

Timing Optimization

Fix Naming

It is important to ensure that the naming styles of variable in the design are appropriatefor the target output language we are using (Verilog in this case). We can firstly see what names need changing:

    report_names -rules verilog

If we are happy with the proposed new names we can perform the name changing process:

    change_names -rules verilog -hierarchy -verbose

Save Out the Design:

This is the final step in the synthesis flow, it allows the designer to transfer the synthesised circuit to the next stage of the design flow. This can be done as follows:

  1. 1. For Place and Route Stage: You need to save the following files:
  2. 2. For post synthesis simulation: You need to save the following files:

The easy way…

Using Design Vision

Simple Script

    analyze -format sv  "../behavioural/qmults.sv ../behavioural/wrap_qmults.sv"

    elaborate wrap_qmults
    create_clock -name master_clock  -period 20 [get_ports Clock]
    compile
    report_area > synth_area.rpt
    report_power > synth_power.rpt
    change_names -rules verilog -hierarchy -verbose

    write -f verilog -hierarchy -output "../gate_level/wrap_qmults.v"

    write_sdc ../constraints/wrap_qmults.sdc
    write_sdf ../gate_level/wrap_qmults.sdf

    exit

Discussion Points

  1. What is the maximum frequency you can achieve? Can you optimise the design further? Explain how
  2. How does optimizing design performance affect its area overhead?
  3. How does optimizing design performance affects its energy dissipation?
  4. How can you resolve hold time violations?

Appendix 1: Optimization using synthesis tool

There are many ways in which a designer can tweak the design at the synthesis stage to obtain the target performance :

Compilation with map_effort high option

Register Balancing

Removing Hierarchy

Choosing High-Speed Implementation for High-level Functional Module

How to Fix Hold Time Violation