ncverilog: 15.10-s002: (c) Copyright 1995-2015 Cadence Design Systems, Inc.
TOOL:	ncverilog	15.10-s002: Started on Feb 01, 2017 at 22:45:23 GMT
ncverilog
	+gui
	+ncaccess+r
	-sv
	wrap_qmults_stim.sv
	wrap_qmults.sv
	qmults.sv
	-v
	/opt/cad/designkits/ams/v410/verilog/c35b4/c35_IOLIB.v
	-s
Recompiling... reason: file './qmults.sv' is newer than expected.
	expected: Wed Feb  1 19:46:09 2017
	actual:   Wed Feb  1 22:45:11 2017
file: qmults.sv
	module worklib.qmults:sv
		errors: 0, warnings: 0
		Caching library 'c35_IOLIB' ....... Done
		Caching library 'worklib' ....... Done
	Elaborating the design hierarchy:
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.qmults:sv <0x6610c035>
			streams:  11, words:  3537
	Building instance specific data structures.
	Loading native compiled code:     .................... Done
	Design hierarchy summary:
		                 Instances  Unique
		Modules:                32       6
		Primitives:             29       1
		Timing outputs:         29       1
		Registers:              15      15
		Scalar wires:           35       -
		Expanded wires:         31       4
		Always blocks:           5       5
		Initial blocks:          1       1
		Cont. assignments:       2       2
		Pseudo assignments:      3       3
		Simulation timescale:  1ps
	Writing initial simulation snapshot: worklib.wrap_qmults_stim:sv
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> 
ncsim> source /opt/cad/soft/cadence/incisiv/tools/inca/files/ncsimrc
ncsim> 
-------------------------------------
Relinquished control to SimVision...
# Restoring simulation environment...
ncsim> input -quiet .reinvoke.sim
ncsim> file delete .reinvoke.sim
ncsim> run
  3,  1,  3,0
  3,  3,  9,0
  3,  7, 21,0
  3, 15, 45,0
  9,  1,  9,0
  9,  3, 27,0
  9,  7, 63,0
  9, 15,  7,1
 21,  1, 21,0
 21,  3, 63,0
 21,  7, 19,1
 21, 15, 59,1
 45,  1, 45,0
Simulation complete via $finish(1) at time 2001 NS + 0
./wrap_qmults_stim.sv:51       $finish;
ncsim> ^C
ncsim> exit
TOOL:	ncverilog	15.10-s002: Exiting on Feb 01, 2017 at 22:50:04 GMT  (total: 00:04:41)