//////////////////////////////////////////////////////////////////////////////////
// qmults_stim.sv 
// SystemVerilog version of test.v from Basel Halak 
//
//////////////////////////////////////////////////////////////////////////////////

module wrap_qmults_stim;

  timeunit 1ns;
  timeprecision 1ps;

  // Inputs
  logic [7:0] multiplicand;
  logic [7:0] multiplier;
  logic start;
  logic Clock;
  logic nReset;
  // Outputs
  wire [7:0] result;
  wire complete;
  wire overflow;

  // Instantiate the Unit Under Test (UUT)
  wrap_qmults uut (
	  .multiplicand, 
	  .multiplier, 
	  .start, 
	  .SDI('0), 
	  .Test('0), 
	  .Clock, 
	  .nReset,
	  .result, 
	  .complete, 
	  .overflow,
	  .SDO()
  );

  logic [10:0]	count;

  initial
    begin
      // Initialize Inputs
      multiplicand = 3;
      multiplier = 0;
      start = 0;
      Clock = 0;
      nReset= 0;
      count = 0;

      #1;
      nReset =1;   

      #2000;
      $finish;
    end

  //clock generator 
  always #1.5 Clock = ~Clock;

  always @(posedge Clock)
    begin
      if (count == 47)
        begin
	  count <= 0;
	  start <= 1'b1;
        end
      else
        begin				
	  count <= count + 1;
	  start <= 1'b0;
        end
    end

  always @(count)
    begin
      if (count == 47)
        begin
	  if ( multiplier > 8'h7 )
            begin
              multiplier <= 1;
              multiplicand = (multiplicand << 1) + 3;
            end
	  else
            multiplier = (multiplier << 1) + 1;
        end
    end

  logic was_going;
  
  always @(posedge Clock)
    begin
      if ( was_going && complete )
        $display ("%d,%d,%d,%b", multiplicand, multiplier, result, overflow);		//	Monitor the stuff we care about
      was_going = ( complete === 0 );
    end


endmodule