/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version   : K-2015.06-SP5
// Date      : Mon Mar  7 13:15:53 2016
/////////////////////////////////////////////////////////////


module cpu ( nME, nReset, SDO, ALE, SDI, RnW, nIRQ, Clock, nOE, Test, Data, 
        nWait );
  inout [15:0] Data;
  input nReset, SDI, nIRQ, Clock, Test, nWait;
  output nME, SDO, ALE, RnW, nOE;
  wire   CORE_nWait, CORE_RnW, CORE_SDO, CORE_Clock, CORE_nReset,
         CPU_core_LoadPC, CPU_core_Control_N21, CPU_core_Control_state, n35,
         n90, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
         n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
         n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n296,
         n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307,
         n308, n309, n310, n311, n312, n313, n314, n315, n316, n317, n318,
         n319, n320, n321, n322, n323, n324, n325, n326, n327, n328, n329,
         n330, n331, n332, n333, n334, n335, n336, n337, n338, n339, n340,
         n341, n342, n343, n344, n345, n346, n347, n348, n349, n350, n351,
         n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362,
         n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
         n374, n375, n376, n377, n378, n379, n380, n381, n382, n383, n384,
         n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395,
         n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406,
         n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417,
         n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, n428,
         n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
         n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450,
         n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461,
         n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472,
         n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
         n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494,
         n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505,
         n506, n507, n508, n509, n510, n511, n512, n513, n514, n515, n516,
         n517, n518, n519, n520, n521, n522, n523, n524, n525, n526, n527,
         n528, n529, n530, n531, n532, n533, n534, n535, n536, n537, n538,
         n539, n540, n541, n542, n543, n544, n545, n546, n547, n548, n549,
         n550, n551, n552, n553, n554, n555, n556, n557, n558, n559, n560,
         n561, n562, n563, n564, n565;
  wire   [15:0] CORE_Data_in;
  wire   [15:0] CORE_Data_out;
  wire   [3:0] CPU_core_Opcode;
  wire   [1:0] CPU_core_Control_sub_state;
  wire   [11:0] CPU_core_Datapath_PC_mux_output;
  wire   [11:0] CPU_core_Datapath_PC;
  wire   [11:0] CPU_core_Datapath_Operand;
  wire   [15:0] CPU_core_Datapath_ACC;
  wire   [15:0] CPU_core_Datapath_ALU_output;

  ICUP PAD_nIRQ ( .PAD(nIRQ) );
  BBC8P PAD_Data_0 ( .A(CORE_Data_out[0]), .EN(n264), .PAD(Data[0]), .Y(
        CORE_Data_in[0]) );
  BBC8P PAD_Data_1 ( .A(CORE_Data_out[1]), .EN(n264), .PAD(Data[1]), .Y(
        CORE_Data_in[1]) );
  BBC8P PAD_Data_2 ( .A(CORE_Data_out[2]), .EN(n264), .PAD(Data[2]), .Y(
        CORE_Data_in[2]) );
  BBC8P PAD_Data_3 ( .A(CORE_Data_out[3]), .EN(n264), .PAD(Data[3]), .Y(
        CORE_Data_in[3]) );
  BBC8P PAD_Data_4 ( .A(CORE_Data_out[4]), .EN(n264), .PAD(Data[4]), .Y(
        CORE_Data_in[4]) );
  BBC8P PAD_Data_5 ( .A(CORE_Data_out[5]), .EN(n264), .PAD(Data[5]), .Y(
        CORE_Data_in[5]) );
  BBC8P PAD_Data_6 ( .A(CORE_Data_out[6]), .EN(n264), .PAD(Data[6]), .Y(
        CORE_Data_in[6]) );
  BBC8P PAD_Data_7 ( .A(CORE_Data_out[7]), .EN(n264), .PAD(Data[7]), .Y(
        CORE_Data_in[7]) );
  BBC8P PAD_Data_8 ( .A(CORE_Data_out[8]), .EN(n264), .PAD(Data[8]), .Y(
        CORE_Data_in[8]) );
  BBC8P PAD_Data_9 ( .A(CORE_Data_out[9]), .EN(n264), .PAD(Data[9]), .Y(
        CORE_Data_in[9]) );
  BBC8P PAD_Data_10 ( .A(CORE_Data_out[10]), .EN(n264), .PAD(Data[10]), .Y(
        CORE_Data_in[10]) );
  BBC8P PAD_Data_11 ( .A(CORE_Data_out[11]), .EN(n264), .PAD(Data[11]), .Y(
        CORE_Data_in[11]) );
  BBC8P PAD_Data_12 ( .A(CORE_Data_out[12]), .EN(n264), .PAD(Data[12]), .Y(
        CORE_Data_in[12]) );
  BBC8P PAD_Data_13 ( .A(CORE_Data_out[13]), .EN(n264), .PAD(Data[13]), .Y(
        CORE_Data_in[13]) );
  BBC8P PAD_Data_14 ( .A(CORE_Data_out[14]), .EN(n264), .PAD(Data[14]), .Y(
        CORE_Data_in[14]) );
  BBC8P PAD_Data_15 ( .A(CORE_Data_out[15]), .EN(n264), .PAD(Data[15]), .Y(
        CORE_Data_in[15]) );
  BU8P PAD_ALE ( .A(n263), .PAD(ALE) );
  BU8P PAD_nME ( .A(n538), .PAD(nME) );
  ICUP PAD_nWait ( .PAD(nWait), .Y(CORE_nWait) );
  BU8P PAD_nOE ( .A(n560), .PAD(nOE) );
  BU8P PAD_RnW ( .A(CORE_RnW), .PAD(RnW) );
  BU8P PAD_SDO ( .A(CORE_SDO), .PAD(SDO) );
  ICP PAD_SDI ( .PAD(SDI), .Y(CORE_SDO) );
  ICP PAD_Test ( .PAD(Test) );
  ICCK2P PAD_Clock ( .PAD(Clock), .Y(CORE_Clock) );
  ICP PAD_nReset ( .PAD(nReset), .Y(CORE_nReset) );
  DFC3 CPU_core_Datapath_ACC_reg_2_ ( .D(CPU_core_Datapath_ALU_output[2]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[2]), .QN(n549)
         );
  DFC3 CPU_core_Datapath_ACC_reg_3_ ( .D(CPU_core_Datapath_ALU_output[3]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[3]), .QN(n555)
         );
  DFC3 CPU_core_Datapath_ACC_reg_4_ ( .D(CPU_core_Datapath_ALU_output[4]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[4]), .QN(n550)
         );
  DFEC1 CPU_core_Datapath_PC_reg_1_ ( .D(CPU_core_Datapath_PC_mux_output[1]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[1]), .QN(n559) );
  DFEC1 CPU_core_Datapath_PC_reg_9_ ( .D(CPU_core_Datapath_PC_mux_output[9]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[9]), .QN(n557) );
  DFEC1 CPU_core_Datapath_PC_reg_7_ ( .D(CPU_core_Datapath_PC_mux_output[7]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[7]), .QN(n541) );
  DFEC1 CPU_core_Datapath_PC_reg_5_ ( .D(CPU_core_Datapath_PC_mux_output[5]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[5]), .QN(n540) );
  DFEC1 CPU_core_Datapath_PC_reg_3_ ( .D(CPU_core_Datapath_PC_mux_output[3]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[3]), .QN(n539) );
  DFEC1 CPU_core_Datapath_PC_reg_0_ ( .D(CPU_core_Datapath_PC_mux_output[0]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[0]), .QN(n536) );
  DFEC1 CPU_core_Datapath_IR_reg_11_ ( .D(CORE_Data_out[11]), .E(n564), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[11]) );
  DFEC1 CPU_core_Datapath_IR_reg_10_ ( .D(CORE_Data_out[10]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[10]) );
  DFEC1 CPU_core_Datapath_PC_reg_11_ ( .D(CPU_core_Datapath_PC_mux_output[11]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[11]) );
  DFEC1 CPU_core_Datapath_IR_reg_9_ ( .D(CORE_Data_out[9]), .E(n564), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[9]) );
  DFEC1 CPU_core_Datapath_PC_reg_10_ ( .D(CPU_core_Datapath_PC_mux_output[10]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[10]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_15_ ( .A(n90), .E(n561), .Q(
        CORE_Data_out[15]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_14_ ( .A(n90), .E(n561), .Q(
        CORE_Data_out[14]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_13_ ( .A(n90), .E(n561), .Q(
        CORE_Data_out[13]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_12_ ( .A(n90), .E(n561), .Q(
        CORE_Data_out[12]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_11_ ( .A(CPU_core_Datapath_Operand[11]), 
        .E(n561), .Q(CORE_Data_out[11]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_15_ ( .A(n90), .E(n562), .Q(
        CORE_Data_out[15]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_14_ ( .A(n90), .E(n562), .Q(
        CORE_Data_out[14]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_13_ ( .A(n90), .E(n562), .Q(
        CORE_Data_out[13]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_12_ ( .A(n90), .E(n562), .Q(
        CORE_Data_out[12]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_11_ ( .A(CPU_core_Datapath_PC[11]), .E(
        n562), .Q(CORE_Data_out[11]) );
  DFEC1 CPU_core_Datapath_IR_reg_8_ ( .D(CORE_Data_out[8]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[8]) );
  DFEC1 CPU_core_Datapath_PC_reg_8_ ( .D(CPU_core_Datapath_PC_mux_output[8]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[8]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_10_ ( .A(CPU_core_Datapath_Operand[10]), 
        .E(n561), .Q(CORE_Data_out[10]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_10_ ( .A(CPU_core_Datapath_PC[10]), .E(
        n562), .Q(CORE_Data_out[10]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_15_ ( .A(CPU_core_Datapath_ACC[15]), .E(
        n35), .Q(CORE_Data_out[15]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_14_ ( .A(CPU_core_Datapath_ACC[14]), .E(
        n35), .Q(CORE_Data_out[14]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_13_ ( .A(CPU_core_Datapath_ACC[13]), .E(
        n35), .Q(CORE_Data_out[13]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_12_ ( .A(CPU_core_Datapath_ACC[12]), .E(
        n35), .Q(CORE_Data_out[12]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_11_ ( .A(CPU_core_Datapath_ACC[11]), .E(
        n35), .Q(CORE_Data_out[11]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_15_ ( .A(CORE_Data_in[15]), .E(n563), 
        .Q(CORE_Data_out[15]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_14_ ( .A(CORE_Data_in[14]), .E(n563), 
        .Q(CORE_Data_out[14]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_13_ ( .A(CORE_Data_in[13]), .E(n563), 
        .Q(CORE_Data_out[13]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_12_ ( .A(CORE_Data_in[12]), .E(n563), 
        .Q(CORE_Data_out[12]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_11_ ( .A(CORE_Data_in[11]), .E(n563), 
        .Q(CORE_Data_out[11]) );
  DFEC1 CPU_core_Datapath_IR_reg_7_ ( .D(CORE_Data_out[7]), .E(n564), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[7]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_9_ ( .A(CPU_core_Datapath_Operand[9]), 
        .E(n561), .Q(CORE_Data_out[9]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_9_ ( .A(CPU_core_Datapath_PC[9]), .E(
        n562), .Q(CORE_Data_out[9]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_10_ ( .A(CPU_core_Datapath_ACC[10]), .E(
        n35), .Q(CORE_Data_out[10]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_10_ ( .A(CORE_Data_in[10]), .E(n563), 
        .Q(CORE_Data_out[10]) );
  DFEC1 CPU_core_Datapath_IR_reg_6_ ( .D(CORE_Data_out[6]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[6]) );
  DFEC1 CPU_core_Datapath_PC_reg_6_ ( .D(CPU_core_Datapath_PC_mux_output[6]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[6]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_8_ ( .A(CPU_core_Datapath_Operand[8]), 
        .E(n561), .Q(CORE_Data_out[8]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_8_ ( .A(CPU_core_Datapath_PC[8]), .E(
        n562), .Q(CORE_Data_out[8]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_9_ ( .A(CPU_core_Datapath_ACC[9]), .E(
        n35), .Q(CORE_Data_out[9]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_9_ ( .A(CORE_Data_in[9]), .E(n563), .Q(
        CORE_Data_out[9]) );
  DFEC1 CPU_core_Datapath_IR_reg_5_ ( .D(CORE_Data_out[5]), .E(n564), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[5]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_7_ ( .A(CPU_core_Datapath_Operand[7]), 
        .E(n561), .Q(CORE_Data_out[7]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_7_ ( .A(CPU_core_Datapath_PC[7]), .E(
        n562), .Q(CORE_Data_out[7]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_8_ ( .A(CPU_core_Datapath_ACC[8]), .E(
        n35), .Q(CORE_Data_out[8]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_8_ ( .A(CORE_Data_in[8]), .E(n563), .Q(
        CORE_Data_out[8]) );
  DFEC1 CPU_core_Datapath_IR_reg_4_ ( .D(CORE_Data_out[4]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[4]) );
  DFEC1 CPU_core_Datapath_PC_reg_4_ ( .D(CPU_core_Datapath_PC_mux_output[4]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[4]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_6_ ( .A(CPU_core_Datapath_Operand[6]), 
        .E(n561), .Q(CORE_Data_out[6]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_6_ ( .A(CPU_core_Datapath_PC[6]), .E(
        n562), .Q(CORE_Data_out[6]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_7_ ( .A(CPU_core_Datapath_ACC[7]), .E(
        n35), .Q(CORE_Data_out[7]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_7_ ( .A(CORE_Data_in[7]), .E(n563), .Q(
        CORE_Data_out[7]) );
  DFEC1 CPU_core_Datapath_IR_reg_3_ ( .D(CORE_Data_out[3]), .E(n564), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[3]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_5_ ( .A(CPU_core_Datapath_Operand[5]), 
        .E(n561), .Q(CORE_Data_out[5]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_5_ ( .A(CPU_core_Datapath_PC[5]), .E(
        n562), .Q(CORE_Data_out[5]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_6_ ( .A(CPU_core_Datapath_ACC[6]), .E(
        n35), .Q(CORE_Data_out[6]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_6_ ( .A(CORE_Data_in[6]), .E(n563), .Q(
        CORE_Data_out[6]) );
  DFEC1 CPU_core_Datapath_IR_reg_1_ ( .D(CORE_Data_out[1]), .E(n564), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[1]) );
  DFEC1 CPU_core_Datapath_IR_reg_2_ ( .D(CORE_Data_out[2]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[2]) );
  DFEC1 CPU_core_Datapath_PC_reg_2_ ( .D(CPU_core_Datapath_PC_mux_output[2]), 
        .E(CPU_core_LoadPC), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Datapath_PC[2]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_4_ ( .A(CPU_core_Datapath_Operand[4]), 
        .E(n561), .Q(CORE_Data_out[4]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_4_ ( .A(CPU_core_Datapath_PC[4]), .E(
        n562), .Q(CORE_Data_out[4]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_5_ ( .A(CPU_core_Datapath_ACC[5]), .E(
        n35), .Q(CORE_Data_out[5]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_5_ ( .A(CORE_Data_in[5]), .E(n563), .Q(
        CORE_Data_out[5]) );
  DFEC1 CPU_core_Datapath_IR_reg_0_ ( .D(CORE_Data_out[0]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_Operand[0]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_3_ ( .A(CPU_core_Datapath_Operand[3]), 
        .E(n561), .Q(CORE_Data_out[3]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_2_ ( .A(CPU_core_Datapath_Operand[2]), 
        .E(n561), .Q(CORE_Data_out[2]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_3_ ( .A(CPU_core_Datapath_PC[3]), .E(
        n562), .Q(CORE_Data_out[3]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_2_ ( .A(CPU_core_Datapath_PC[2]), .E(
        n562), .Q(CORE_Data_out[2]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_4_ ( .A(CPU_core_Datapath_ACC[4]), .E(
        n35), .Q(CORE_Data_out[4]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_3_ ( .A(CPU_core_Datapath_ACC[3]), .E(
        n35), .Q(CORE_Data_out[3]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_4_ ( .A(CORE_Data_in[4]), .E(n563), .Q(
        CORE_Data_out[4]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_3_ ( .A(CORE_Data_in[3]), .E(n563), .Q(
        CORE_Data_out[3]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_1_ ( .A(CPU_core_Datapath_Operand[1]), 
        .E(n561), .Q(CORE_Data_out[1]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_1_ ( .A(CPU_core_Datapath_PC[1]), .E(
        n562), .Q(CORE_Data_out[1]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_2_ ( .A(CPU_core_Datapath_ACC[2]), .E(
        n35), .Q(CORE_Data_out[2]) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_1_ ( .A(CPU_core_Datapath_ACC[1]), .E(
        n35), .Q(CORE_Data_out[1]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_1_ ( .A(CORE_Data_in[1]), .E(n563), .Q(
        CORE_Data_out[1]) );
  BUFE2 CPU_core_Datapath_SysBus_tri_0_ ( .A(CPU_core_Datapath_Operand[0]), 
        .E(n561), .Q(CORE_Data_out[0]) );
  BUFE2 CPU_core_Datapath_SysBus_tri2_0_ ( .A(CPU_core_Datapath_PC[0]), .E(
        n562), .Q(CORE_Data_out[0]) );
  DFC1 CPU_core_Datapath_ACC_reg_8_ ( .D(CPU_core_Datapath_ALU_output[8]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[8]), .QN(n553)
         );
  DFEC1 CPU_core_Datapath_IR_reg_13_ ( .D(CORE_Data_out[13]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Opcode[1]), .QN(n543) );
  DFC1 CPU_core_Datapath_ACC_reg_11_ ( .D(CPU_core_Datapath_ALU_output[11]), 
        .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[11]), .QN(
        n548) );
  DFC1 CPU_core_Datapath_ACC_reg_12_ ( .D(CPU_core_Datapath_ALU_output[12]), 
        .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[12]), .QN(
        n554) );
  DFC1 CPU_core_Datapath_ACC_reg_13_ ( .D(CPU_core_Datapath_ALU_output[13]), 
        .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[13]), .QN(
        n544) );
  DFC1 CPU_core_Datapath_ACC_reg_14_ ( .D(CPU_core_Datapath_ALU_output[14]), 
        .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[14]), .QN(
        n545) );
  DFC1 CPU_core_Datapath_ACC_reg_15_ ( .D(CPU_core_Datapath_ALU_output[15]), 
        .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[15]), .QN(
        n535) );
  DFEC1 CPU_core_Datapath_IR_reg_15_ ( .D(CORE_Data_out[15]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Opcode[3]), .QN(n534) );
  DFC1 CPU_core_Datapath_ACC_reg_0_ ( .D(CPU_core_Datapath_ALU_output[0]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[0]), .QN(n542)
         );
  DFC1 CPU_core_Datapath_ACC_reg_1_ ( .D(CPU_core_Datapath_ALU_output[1]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[1]), .QN(n558)
         );
  DFC1 CPU_core_Datapath_ACC_reg_5_ ( .D(CPU_core_Datapath_ALU_output[5]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[5]), .QN(n551)
         );
  DFC1 CPU_core_Datapath_ACC_reg_7_ ( .D(CPU_core_Datapath_ALU_output[7]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[7]), .QN(n556)
         );
  DFC1 CPU_core_Datapath_ACC_reg_9_ ( .D(CPU_core_Datapath_ALU_output[9]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[9]), .QN(n546)
         );
  DFC1 CPU_core_Datapath_ACC_reg_10_ ( .D(CPU_core_Datapath_ALU_output[10]), 
        .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[10]), .QN(
        n547) );
  BUFE2 CPU_core_Datapath_SysBus_tri3_0_ ( .A(CPU_core_Datapath_ACC[0]), .E(
        n35), .Q(CORE_Data_out[0]) );
  TFEC1 CPU_core_Control_state_reg ( .T(n565), .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Control_state), .QN(n533) );
  DFEC1 CPU_core_Datapath_IR_reg_14_ ( .D(CORE_Data_out[14]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Opcode[2]), .QN(n537) );
  DFEC1 CPU_core_Control_sub_state_reg_1_ ( .D(CPU_core_Control_sub_state[0]), 
        .E(CPU_core_Control_N21), .C(CORE_Clock), .RN(CORE_nReset), .Q(
        CPU_core_Control_sub_state[1]), .QN(n532) );
  DFEC1 CPU_core_Control_sub_state_reg_0_ ( .D(n532), .E(CPU_core_Control_N21), 
        .C(CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Control_sub_state[0]), 
        .QN(n538) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_2_ ( .A(CORE_Data_in[2]), .E(n563), .Q(
        CORE_Data_out[2]) );
  BUFE2 CPU_core_Datapath_SysBus_tri4_0_ ( .A(CORE_Data_in[0]), .E(n563), .Q(
        CORE_Data_out[0]) );
  DFEC3 CPU_core_Datapath_IR_reg_12_ ( .D(CORE_Data_out[12]), .E(n330), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Opcode[0]) );
  DFC1 CPU_core_Datapath_ACC_reg_6_ ( .D(CPU_core_Datapath_ALU_output[6]), .C(
        CORE_Clock), .RN(CORE_nReset), .Q(CPU_core_Datapath_ACC[6]), .QN(n552)
         );
  BUF2 U175 ( .A(n530), .Q(n525) );
  NOR23 U176 ( .A(n538), .B(n560), .Q(n563) );
  NOR21 U177 ( .A(n320), .B(n318), .Q(n307) );
  NAND20 U178 ( .A(n385), .B(CPU_core_Datapath_ACC[4]), .Q(n397) );
  XOR20 U179 ( .A(n503), .B(CORE_Data_out[5]), .Q(n413) );
  NAND20 U180 ( .A(n277), .B(CPU_core_Datapath_PC[6]), .Q(n280) );
  NOR20 U181 ( .A(n280), .B(n541), .Q(n284) );
  NOR20 U182 ( .A(n532), .B(CPU_core_Control_sub_state[0]), .Q(n565) );
  INV2 U183 ( .A(n372), .Q(n373) );
  INV2 U184 ( .A(n410), .Q(n424) );
  INV2 U185 ( .A(n384), .Q(n399) );
  INV2 U186 ( .A(n308), .Q(n343) );
  INV2 U187 ( .A(n341), .Q(n342) );
  NOR20 U188 ( .A(CPU_core_Datapath_ACC[6]), .B(n411), .Q(n410) );
  XOR20 U189 ( .A(n503), .B(CORE_Data_out[6]), .Q(n411) );
  NOR22 U190 ( .A(n349), .B(n348), .Q(n513) );
  INV2 U191 ( .A(n321), .Q(n511) );
  INV15 U192 ( .A(n560), .Q(n264) );
  NAND22 U193 ( .A(n306), .B(n305), .Q(n318) );
  INV2 U194 ( .A(n302), .Q(n306) );
  INV2 U195 ( .A(n565), .Q(n294) );
  AOI211 U196 ( .A(n519), .B(n518), .C(n517), .Q(n520) );
  INV1 U197 ( .A(n502), .Q(CPU_core_Datapath_ALU_output[14]) );
  XOR21 U198 ( .A(n508), .B(n507), .Q(n519) );
  INV1 U199 ( .A(n491), .Q(CPU_core_Datapath_ALU_output[13]) );
  INV1 U200 ( .A(n482), .Q(CPU_core_Datapath_ALU_output[12]) );
  INV1 U201 ( .A(n473), .Q(CPU_core_Datapath_ALU_output[11]) );
  ADD31 U202 ( .A(n466), .B(CPU_core_Datapath_ACC[10]), .CI(n465), .CO(n474), 
        .S(n463) );
  INV3 U203 ( .A(n426), .Q(n438) );
  OAI211 U204 ( .A(n361), .B(n360), .C(n359), .Q(n375) );
  INV2 U205 ( .A(n357), .Q(n374) );
  NOR21 U206 ( .A(CPU_core_Datapath_ACC[3]), .B(n370), .Q(n388) );
  NAND21 U207 ( .A(n411), .B(CPU_core_Datapath_ACC[6]), .Q(n422) );
  NAND21 U208 ( .A(n370), .B(CPU_core_Datapath_ACC[3]), .Q(n386) );
  NOR21 U209 ( .A(CPU_core_Datapath_ACC[1]), .B(n345), .Q(n360) );
  XOR21 U210 ( .A(CORE_Data_out[0]), .B(n503), .Q(n344) );
  INV2 U211 ( .A(n512), .Q(n495) );
  NAND21 U212 ( .A(CPU_core_Datapath_PC[10]), .B(n435), .Q(n434) );
  XOR21 U213 ( .A(n503), .B(CORE_Data_out[1]), .Q(n345) );
  NAND21 U214 ( .A(n314), .B(n320), .Q(n348) );
  NAND21 U215 ( .A(n284), .B(CPU_core_Datapath_PC[8]), .Q(n287) );
  INV3 U216 ( .A(n307), .Q(n310) );
  INV1 U217 ( .A(n318), .Q(n314) );
  NAND21 U218 ( .A(n339), .B(n338), .Q(n340) );
  INV2 U219 ( .A(n317), .Q(n494) );
  CLKIN3 U220 ( .A(n316), .Q(n349) );
  NAND21 U221 ( .A(n316), .B(n543), .Q(n321) );
  NAND21 U222 ( .A(n299), .B(n298), .Q(n301) );
  BUF2 U223 ( .A(n564), .Q(n330) );
  INV1 U224 ( .A(n304), .Q(n305) );
  NAND21 U225 ( .A(n528), .B(CPU_core_Datapath_PC[4]), .Q(n527) );
  CLKIN3 U226 ( .A(n300), .Q(n337) );
  NOR21 U227 ( .A(n534), .B(n303), .Q(n312) );
  NOR21 U228 ( .A(n266), .B(n265), .Q(n267) );
  NAND31 U229 ( .A(CPU_core_Opcode[3]), .B(CPU_core_Control_state), .C(
        CPU_core_Opcode[0]), .Q(n266) );
  NAND31 U230 ( .A(CPU_core_Datapath_PC[0]), .B(CPU_core_Datapath_PC[1]), .C(
        CPU_core_Datapath_PC[2]), .Q(n521) );
  INV2 U231 ( .A(n520), .Q(CPU_core_Datapath_ALU_output[15]) );
  ADD32 U232 ( .A(n506), .B(CPU_core_Datapath_ACC[14]), .CI(n505), .CO(n507), 
        .S(n501) );
  ADD32 U233 ( .A(n493), .B(CPU_core_Datapath_ACC[13]), .CI(n492), .CO(n505), 
        .S(n490) );
  ADD32 U234 ( .A(n439), .B(CPU_core_Datapath_ACC[7]), .CI(n438), .CO(n447), 
        .S(n432) );
  AOI212 U235 ( .A(n425), .B(n424), .C(n423), .Q(n426) );
  ADD32 U236 ( .A(n448), .B(CPU_core_Datapath_ACC[8]), .CI(n447), .CO(n456), 
        .S(n445) );
  NOR21 U237 ( .A(CPU_core_Datapath_ACC[4]), .B(n385), .Q(n384) );
  XOR20 U238 ( .A(n503), .B(CORE_Data_out[10]), .Q(n466) );
  NAND22 U239 ( .A(n358), .B(CPU_core_Datapath_ACC[2]), .Q(n372) );
  NOR21 U240 ( .A(CPU_core_Datapath_ACC[0]), .B(n503), .Q(n308) );
  XOR20 U241 ( .A(n503), .B(CORE_Data_out[9]), .Q(n457) );
  INV3 U242 ( .A(n401), .Q(n412) );
  XOR21 U243 ( .A(n503), .B(CORE_Data_out[4]), .Q(n385) );
  XOR21 U244 ( .A(n503), .B(CORE_Data_out[2]), .Q(n358) );
  NOR20 U245 ( .A(n313), .B(n337), .Q(n317) );
  NOR21 U246 ( .A(CPU_core_Opcode[0]), .B(n302), .Q(n316) );
  NOR22 U247 ( .A(n301), .B(n337), .Q(n320) );
  INV0 U248 ( .A(n397), .Q(n398) );
  XOR20 U249 ( .A(n503), .B(CORE_Data_out[8]), .Q(n448) );
  AOI210 U250 ( .A(CORE_Data_out[8]), .B(n510), .C(n509), .Q(n443) );
  NOR20 U251 ( .A(n527), .B(n540), .Q(n277) );
  NOR20 U252 ( .A(n287), .B(n557), .Q(n435) );
  NAND40 U253 ( .A(n335), .B(n535), .C(n542), .D(n334), .Q(n336) );
  AOI210 U254 ( .A(CORE_Data_out[10]), .B(n510), .C(n509), .Q(n461) );
  AOI210 U255 ( .A(CORE_Data_out[9]), .B(n510), .C(n509), .Q(n452) );
  XOR20 U256 ( .A(n503), .B(CORE_Data_out[7]), .Q(n439) );
  AOI210 U257 ( .A(n513), .B(CPU_core_Datapath_ACC[6]), .C(n427), .Q(n428) );
  NAND20 U258 ( .A(n424), .B(n422), .Q(n414) );
  AOI210 U259 ( .A(n513), .B(CPU_core_Datapath_ACC[5]), .C(n415), .Q(n416) );
  AOI210 U260 ( .A(CORE_Data_out[6]), .B(n510), .C(n509), .Q(n418) );
  NAND20 U261 ( .A(CORE_Data_out[6]), .B(n511), .Q(n417) );
  AOI210 U262 ( .A(n513), .B(CPU_core_Datapath_ACC[4]), .C(n403), .Q(n404) );
  AOI210 U263 ( .A(CORE_Data_out[5]), .B(n510), .C(n402), .Q(n406) );
  NAND20 U264 ( .A(n399), .B(n397), .Q(n389) );
  AOI210 U265 ( .A(n513), .B(CPU_core_Datapath_ACC[3]), .C(n390), .Q(n391) );
  AOI210 U266 ( .A(CORE_Data_out[4]), .B(n510), .C(n402), .Q(n393) );
  NAND20 U267 ( .A(CORE_Data_out[4]), .B(n511), .Q(n392) );
  NAND20 U268 ( .A(n371), .B(n386), .Q(n376) );
  INV0 U269 ( .A(n388), .Q(n371) );
  AOI210 U270 ( .A(n513), .B(CPU_core_Datapath_ACC[2]), .C(n377), .Q(n378) );
  NAND20 U271 ( .A(CORE_Data_out[3]), .B(n511), .Q(n379) );
  AOI210 U272 ( .A(n513), .B(CPU_core_Datapath_ACC[1]), .C(n363), .Q(n364) );
  NAND20 U273 ( .A(CORE_Data_out[2]), .B(n511), .Q(n365) );
  NAND20 U274 ( .A(n374), .B(n372), .Q(n362) );
  INV0 U275 ( .A(n360), .Q(n346) );
  NAND20 U276 ( .A(CORE_Data_out[1]), .B(n511), .Q(n352) );
  NAND20 U277 ( .A(n343), .B(n341), .Q(n309) );
  AOI210 U278 ( .A(n324), .B(n323), .C(n542), .Q(n325) );
  INV0 U279 ( .A(n509), .Q(n323) );
  XOR20 U280 ( .A(CPU_core_Datapath_ACC[15]), .B(n504), .Q(n508) );
  XOR20 U281 ( .A(n503), .B(CORE_Data_out[15]), .Q(n504) );
  AOI210 U282 ( .A(CORE_Data_out[15]), .B(n510), .C(n509), .Q(n516) );
  NAND20 U283 ( .A(CORE_Data_out[15]), .B(n511), .Q(n515) );
  XOR20 U284 ( .A(n503), .B(CORE_Data_out[14]), .Q(n506) );
  AOI210 U285 ( .A(n513), .B(CPU_core_Datapath_ACC[13]), .C(n496), .Q(n497) );
  XOR20 U286 ( .A(n503), .B(CORE_Data_out[13]), .Q(n493) );
  AOI210 U287 ( .A(CORE_Data_out[13]), .B(n510), .C(n509), .Q(n488) );
  ADD31 U288 ( .A(n484), .B(CPU_core_Datapath_ACC[12]), .CI(n483), .CO(n492), 
        .S(n481) );
  XOR20 U289 ( .A(n503), .B(CORE_Data_out[12]), .Q(n484) );
  AOI210 U290 ( .A(CORE_Data_out[12]), .B(n510), .C(n509), .Q(n479) );
  ADD31 U291 ( .A(n475), .B(CPU_core_Datapath_ACC[11]), .CI(n474), .CO(n483), 
        .S(n472) );
  XOR20 U292 ( .A(n503), .B(CORE_Data_out[11]), .Q(n475) );
  AOI210 U293 ( .A(CORE_Data_out[11]), .B(n510), .C(n509), .Q(n470) );
  INV0 U294 ( .A(n446), .Q(CPU_core_Datapath_ALU_output[8]) );
  AOI210 U295 ( .A(n445), .B(n518), .C(n444), .Q(n446) );
  OAI2110 U296 ( .A(n553), .B(n443), .C(n442), .D(n441), .Q(n444) );
  NAND20 U297 ( .A(CORE_Data_out[8]), .B(n511), .Q(n442) );
  XOR20 U298 ( .A(CPU_core_Datapath_PC[11]), .B(n434), .Q(n292) );
  NOR20 U299 ( .A(n288), .B(CPU_core_Datapath_PC[9]), .Q(n290) );
  INV0 U300 ( .A(n464), .Q(CPU_core_Datapath_ALU_output[10]) );
  OAI2110 U301 ( .A(n547), .B(n461), .C(n460), .D(n459), .Q(n462) );
  INV0 U302 ( .A(n455), .Q(CPU_core_Datapath_ALU_output[9]) );
  AOI210 U303 ( .A(n454), .B(n518), .C(n453), .Q(n455) );
  OAI2110 U304 ( .A(n546), .B(n452), .C(n451), .D(n450), .Q(n453) );
  NAND20 U305 ( .A(CORE_Data_out[9]), .B(n511), .Q(n451) );
  INV0 U306 ( .A(n433), .Q(CPU_core_Datapath_ALU_output[7]) );
  AOI210 U307 ( .A(n432), .B(n518), .C(n431), .Q(n433) );
  OAI2110 U308 ( .A(n556), .B(n430), .C(n429), .D(n428), .Q(n431) );
  NAND20 U309 ( .A(CORE_Data_out[7]), .B(n511), .Q(n429) );
  AOI210 U310 ( .A(n420), .B(n518), .C(n419), .Q(n421) );
  OAI2110 U311 ( .A(n552), .B(n418), .C(n417), .D(n416), .Q(n419) );
  XNR20 U312 ( .A(n414), .B(n425), .Q(n420) );
  AOI210 U313 ( .A(n408), .B(n518), .C(n407), .Q(n409) );
  OAI2110 U314 ( .A(n551), .B(n406), .C(n405), .D(n404), .Q(n407) );
  NAND20 U315 ( .A(CORE_Data_out[5]), .B(n511), .Q(n405) );
  AOI210 U316 ( .A(n395), .B(n518), .C(n394), .Q(n396) );
  OAI2110 U317 ( .A(n550), .B(n393), .C(n392), .D(n391), .Q(n394) );
  XNR20 U318 ( .A(n389), .B(n400), .Q(n395) );
  AOI210 U319 ( .A(n382), .B(n518), .C(n381), .Q(n383) );
  OAI2110 U320 ( .A(n555), .B(n380), .C(n379), .D(n378), .Q(n381) );
  XOR20 U321 ( .A(n376), .B(n387), .Q(n382) );
  AOI210 U322 ( .A(n368), .B(n518), .C(n367), .Q(n369) );
  XNR20 U323 ( .A(n362), .B(n375), .Q(n368) );
  OAI2110 U324 ( .A(n549), .B(n366), .C(n365), .D(n364), .Q(n367) );
  AOI210 U325 ( .A(n355), .B(n518), .C(n354), .Q(n356) );
  OAI2110 U326 ( .A(n558), .B(n353), .C(n352), .D(n351), .Q(n354) );
  XOR20 U327 ( .A(n361), .B(n347), .Q(n355) );
  XNR20 U328 ( .A(n344), .B(n309), .Q(n311) );
  OAI2110 U329 ( .A(n535), .B(n516), .C(n515), .D(n514), .Q(n517) );
  AOI210 U330 ( .A(n501), .B(n518), .C(n500), .Q(n502) );
  OAI2110 U331 ( .A(n545), .B(n499), .C(n498), .D(n497), .Q(n500) );
  NAND20 U332 ( .A(CORE_Data_out[14]), .B(n511), .Q(n498) );
  AOI210 U333 ( .A(n490), .B(n518), .C(n489), .Q(n491) );
  OAI2110 U334 ( .A(n544), .B(n488), .C(n487), .D(n486), .Q(n489) );
  NAND20 U335 ( .A(CORE_Data_out[13]), .B(n511), .Q(n487) );
  AOI210 U336 ( .A(n481), .B(n518), .C(n480), .Q(n482) );
  OAI2110 U337 ( .A(n554), .B(n479), .C(n478), .D(n477), .Q(n480) );
  NAND20 U338 ( .A(CORE_Data_out[12]), .B(n511), .Q(n478) );
  AOI210 U339 ( .A(n472), .B(n518), .C(n471), .Q(n473) );
  OAI2110 U340 ( .A(n548), .B(n470), .C(n469), .D(n468), .Q(n471) );
  NAND20 U341 ( .A(CORE_Data_out[11]), .B(n511), .Q(n469) );
  INV6 U342 ( .A(n268), .Q(n560) );
  NAND22 U343 ( .A(n565), .B(n533), .Q(n530) );
  NOR21 U344 ( .A(CPU_core_Control_state), .B(n296), .Q(n564) );
  NAND20 U345 ( .A(CORE_Data_out[0]), .B(n510), .Q(n324) );
  AOI210 U346 ( .A(CORE_Data_out[1]), .B(n510), .C(n402), .Q(n353) );
  AOI210 U347 ( .A(CORE_Data_out[2]), .B(n510), .C(n402), .Q(n366) );
  AOI210 U348 ( .A(CORE_Data_out[3]), .B(n510), .C(n402), .Q(n380) );
  NOR22 U349 ( .A(n315), .B(n314), .Q(n510) );
  INV0 U350 ( .A(n312), .Q(n299) );
  XNR20 U351 ( .A(CPU_core_Opcode[2]), .B(n534), .Q(n297) );
  INV0 U352 ( .A(n422), .Q(n423) );
  XOR21 U353 ( .A(n503), .B(CORE_Data_out[3]), .Q(n370) );
  NOR21 U354 ( .A(n533), .B(n296), .Q(n300) );
  NAND20 U355 ( .A(CORE_Data_out[10]), .B(n511), .Q(n460) );
  AOI210 U356 ( .A(CORE_Data_out[7]), .B(n510), .C(n509), .Q(n430) );
  NAND20 U357 ( .A(n346), .B(n359), .Q(n347) );
  AOI210 U358 ( .A(CORE_Data_out[14]), .B(n510), .C(n509), .Q(n499) );
  NOR22 U359 ( .A(n532), .B(n267), .Q(n268) );
  NOR20 U360 ( .A(n521), .B(n539), .Q(n528) );
  AOI210 U361 ( .A(n463), .B(n518), .C(n462), .Q(n464) );
  AOI2110 U362 ( .A(CORE_Data_out[0]), .B(n511), .C(n326), .D(n325), .Q(n327)
         );
  OAI210 U363 ( .A(n437), .B(n525), .C(n436), .Q(
        CPU_core_Datapath_PC_mux_output[10]) );
  INV0 U364 ( .A(n369), .Q(CPU_core_Datapath_ALU_output[2]) );
  LOGIC0 U365 ( .Q(n90) );
  NAND22 U366 ( .A(CPU_core_Opcode[2]), .B(CPU_core_Opcode[1]), .Q(n265) );
  INV0 U367 ( .A(n521), .Q(n269) );
  NOR20 U368 ( .A(n269), .B(CPU_core_Datapath_PC[3]), .Q(n271) );
  NAND20 U369 ( .A(n525), .B(CPU_core_Datapath_Operand[3]), .Q(n270) );
  OAI310 U370 ( .A(n528), .B(n271), .C(n525), .D(n270), .Q(
        CPU_core_Datapath_PC_mux_output[3]) );
  NOR20 U371 ( .A(n536), .B(n559), .Q(n522) );
  NOR20 U372 ( .A(CPU_core_Datapath_PC[0]), .B(CPU_core_Datapath_PC[1]), .Q(
        n273) );
  NAND20 U373 ( .A(n525), .B(CPU_core_Datapath_Operand[1]), .Q(n272) );
  OAI310 U374 ( .A(n522), .B(n273), .C(n525), .D(n272), .Q(
        CPU_core_Datapath_PC_mux_output[1]) );
  INV0 U375 ( .A(n527), .Q(n274) );
  NOR20 U376 ( .A(n274), .B(CPU_core_Datapath_PC[5]), .Q(n276) );
  NAND20 U377 ( .A(n525), .B(CPU_core_Datapath_Operand[5]), .Q(n275) );
  OAI310 U378 ( .A(n277), .B(n276), .C(n525), .D(n275), .Q(
        CPU_core_Datapath_PC_mux_output[5]) );
  OAI210 U379 ( .A(n277), .B(CPU_core_Datapath_PC[6]), .C(n280), .Q(n279) );
  NAND20 U380 ( .A(n525), .B(CPU_core_Datapath_Operand[6]), .Q(n278) );
  OAI210 U381 ( .A(n279), .B(n525), .C(n278), .Q(
        CPU_core_Datapath_PC_mux_output[6]) );
  INV0 U382 ( .A(n280), .Q(n281) );
  NOR20 U383 ( .A(n281), .B(CPU_core_Datapath_PC[7]), .Q(n283) );
  NAND20 U384 ( .A(n525), .B(CPU_core_Datapath_Operand[7]), .Q(n282) );
  OAI310 U385 ( .A(n284), .B(n283), .C(n525), .D(n282), .Q(
        CPU_core_Datapath_PC_mux_output[7]) );
  OAI210 U386 ( .A(n284), .B(CPU_core_Datapath_PC[8]), .C(n287), .Q(n286) );
  NAND20 U387 ( .A(n525), .B(CPU_core_Datapath_Operand[8]), .Q(n285) );
  OAI210 U388 ( .A(n286), .B(n525), .C(n285), .Q(
        CPU_core_Datapath_PC_mux_output[8]) );
  INV0 U389 ( .A(n287), .Q(n288) );
  NAND20 U390 ( .A(n525), .B(CPU_core_Datapath_Operand[9]), .Q(n289) );
  OAI310 U391 ( .A(n435), .B(n290), .C(n525), .D(n289), .Q(
        CPU_core_Datapath_PC_mux_output[9]) );
  NAND20 U392 ( .A(n525), .B(CPU_core_Datapath_Operand[11]), .Q(n291) );
  OAI210 U393 ( .A(n530), .B(n292), .C(n291), .Q(
        CPU_core_Datapath_PC_mux_output[11]) );
  NOR22 U394 ( .A(n533), .B(CPU_core_Control_sub_state[1]), .Q(n561) );
  NOR22 U395 ( .A(CPU_core_Control_state), .B(CPU_core_Control_sub_state[1]), 
        .Q(n562) );
  NAND22 U396 ( .A(CPU_core_Opcode[1]), .B(CPU_core_Opcode[0]), .Q(n303) );
  NOR20 U397 ( .A(n533), .B(n532), .Q(n293) );
  NAND31 U398 ( .A(n312), .B(n293), .C(CPU_core_Opcode[2]), .Q(CORE_RnW) );
  NAND24 U399 ( .A(CORE_RnW), .B(n294), .Q(n35) );
  NAND31 U400 ( .A(CPU_core_Control_sub_state[0]), .B(
        CPU_core_Control_sub_state[1]), .C(CORE_nWait), .Q(n296) );
  NAND22 U401 ( .A(n297), .B(n300), .Q(n302) );
  OAI220 U402 ( .A(n537), .B(n303), .C(n534), .D(CPU_core_Opcode[2]), .Q(n298)
         );
  OAI210 U403 ( .A(CPU_core_Opcode[1]), .B(CPU_core_Opcode[0]), .C(n303), .Q(
        n304) );
  NOR24 U404 ( .A(n349), .B(n310), .Q(n503) );
  NAND22 U405 ( .A(n503), .B(CPU_core_Datapath_ACC[0]), .Q(n341) );
  INV3 U406 ( .A(n310), .Q(n518) );
  NAND20 U407 ( .A(n311), .B(n518), .Q(n328) );
  NOR20 U408 ( .A(n316), .B(n348), .Q(n512) );
  NAND20 U409 ( .A(n312), .B(n537), .Q(n313) );
  OAI220 U410 ( .A(n495), .B(CPU_core_Datapath_ACC[0]), .C(n494), .D(n558), 
        .Q(n326) );
  INV0 U411 ( .A(n320), .Q(n315) );
  NOR20 U412 ( .A(n317), .B(n316), .Q(n319) );
  NAND20 U413 ( .A(n319), .B(n318), .Q(n322) );
  IMUX21 U414 ( .A(n322), .B(n321), .S(n320), .Q(n402) );
  BUF2 U415 ( .A(n402), .Q(n509) );
  NAND20 U416 ( .A(n328), .B(n327), .Q(CPU_core_Datapath_ALU_output[0]) );
  NOR20 U417 ( .A(CPU_core_Control_sub_state[1]), .B(
        CPU_core_Control_sub_state[0]), .Q(n263) );
  INV0 U418 ( .A(CORE_nWait), .Q(n329) );
  NAND30 U419 ( .A(CPU_core_Control_sub_state[0]), .B(
        CPU_core_Control_sub_state[1]), .C(n329), .Q(CPU_core_Control_N21) );
  NOR40 U420 ( .A(CPU_core_Datapath_ACC[3]), .B(CPU_core_Datapath_ACC[4]), .C(
        CPU_core_Datapath_ACC[5]), .D(CPU_core_Datapath_ACC[6]), .Q(n332) );
  NOR40 U421 ( .A(CPU_core_Datapath_ACC[7]), .B(CPU_core_Datapath_ACC[8]), .C(
        CPU_core_Datapath_ACC[9]), .D(CPU_core_Datapath_ACC[10]), .Q(n331) );
  NAND30 U422 ( .A(CPU_core_Opcode[1]), .B(n332), .C(n331), .Q(n333) );
  NOR30 U423 ( .A(n333), .B(CPU_core_Datapath_ACC[14]), .C(
        CPU_core_Datapath_ACC[13]), .Q(n335) );
  NOR40 U424 ( .A(CPU_core_Datapath_ACC[12]), .B(CPU_core_Datapath_ACC[11]), 
        .C(CPU_core_Datapath_ACC[2]), .D(CPU_core_Datapath_ACC[1]), .Q(n334)
         );
  XNR20 U425 ( .A(CPU_core_Opcode[0]), .B(n336), .Q(n339) );
  NOR30 U426 ( .A(CPU_core_Opcode[3]), .B(CPU_core_Opcode[2]), .C(n337), .Q(
        n338) );
  NAND22 U427 ( .A(n340), .B(n525), .Q(CPU_core_LoadPC) );
  AOI212 U428 ( .A(n344), .B(n343), .C(n342), .Q(n361) );
  NAND21 U429 ( .A(n345), .B(CPU_core_Datapath_ACC[1]), .Q(n359) );
  OAI220 U430 ( .A(n495), .B(CPU_core_Datapath_ACC[1]), .C(n494), .D(n549), 
        .Q(n350) );
  AOI210 U431 ( .A(n513), .B(CPU_core_Datapath_ACC[0]), .C(n350), .Q(n351) );
  INV0 U432 ( .A(n356), .Q(CPU_core_Datapath_ALU_output[1]) );
  NOR21 U433 ( .A(CPU_core_Datapath_ACC[2]), .B(n358), .Q(n357) );
  OAI220 U434 ( .A(n495), .B(CPU_core_Datapath_ACC[2]), .C(n494), .D(n555), 
        .Q(n363) );
  AOI212 U435 ( .A(n375), .B(n374), .C(n373), .Q(n387) );
  OAI220 U436 ( .A(n495), .B(CPU_core_Datapath_ACC[3]), .C(n494), .D(n550), 
        .Q(n377) );
  INV0 U437 ( .A(n383), .Q(CPU_core_Datapath_ALU_output[3]) );
  OAI212 U438 ( .A(n388), .B(n387), .C(n386), .Q(n400) );
  OAI220 U439 ( .A(n495), .B(CPU_core_Datapath_ACC[4]), .C(n494), .D(n551), 
        .Q(n390) );
  INV0 U440 ( .A(n396), .Q(CPU_core_Datapath_ALU_output[4]) );
  AOI212 U441 ( .A(n400), .B(n399), .C(n398), .Q(n401) );
  OAI220 U442 ( .A(n495), .B(CPU_core_Datapath_ACC[5]), .C(n494), .D(n552), 
        .Q(n403) );
  INV0 U443 ( .A(n409), .Q(CPU_core_Datapath_ALU_output[5]) );
  ADD32 U444 ( .A(n413), .B(CPU_core_Datapath_ACC[5]), .CI(n412), .CO(n425), 
        .S(n408) );
  OAI220 U445 ( .A(n495), .B(CPU_core_Datapath_ACC[6]), .C(n494), .D(n556), 
        .Q(n415) );
  INV0 U446 ( .A(n421), .Q(CPU_core_Datapath_ALU_output[6]) );
  OAI220 U447 ( .A(n495), .B(CPU_core_Datapath_ACC[7]), .C(n494), .D(n553), 
        .Q(n427) );
  OAI210 U448 ( .A(CPU_core_Datapath_PC[10]), .B(n435), .C(n434), .Q(n437) );
  NAND20 U449 ( .A(n525), .B(CPU_core_Datapath_Operand[10]), .Q(n436) );
  OAI220 U450 ( .A(n495), .B(CPU_core_Datapath_ACC[8]), .C(n494), .D(n546), 
        .Q(n440) );
  AOI210 U451 ( .A(n513), .B(CPU_core_Datapath_ACC[7]), .C(n440), .Q(n441) );
  OAI220 U452 ( .A(n495), .B(CPU_core_Datapath_ACC[9]), .C(n494), .D(n547), 
        .Q(n449) );
  AOI210 U453 ( .A(n513), .B(CPU_core_Datapath_ACC[8]), .C(n449), .Q(n450) );
  ADD32 U454 ( .A(n457), .B(CPU_core_Datapath_ACC[9]), .CI(n456), .CO(n465), 
        .S(n454) );
  OAI220 U455 ( .A(n495), .B(CPU_core_Datapath_ACC[10]), .C(n494), .D(n548), 
        .Q(n458) );
  AOI210 U456 ( .A(n513), .B(CPU_core_Datapath_ACC[9]), .C(n458), .Q(n459) );
  OAI220 U457 ( .A(n495), .B(CPU_core_Datapath_ACC[11]), .C(n494), .D(n554), 
        .Q(n467) );
  AOI210 U458 ( .A(n513), .B(CPU_core_Datapath_ACC[10]), .C(n467), .Q(n468) );
  OAI220 U459 ( .A(n495), .B(CPU_core_Datapath_ACC[12]), .C(n494), .D(n544), 
        .Q(n476) );
  AOI210 U460 ( .A(n513), .B(CPU_core_Datapath_ACC[11]), .C(n476), .Q(n477) );
  OAI220 U461 ( .A(n495), .B(CPU_core_Datapath_ACC[13]), .C(n494), .D(n545), 
        .Q(n485) );
  AOI210 U462 ( .A(n513), .B(CPU_core_Datapath_ACC[12]), .C(n485), .Q(n486) );
  OAI220 U463 ( .A(n495), .B(CPU_core_Datapath_ACC[14]), .C(n494), .D(n535), 
        .Q(n496) );
  AOI220 U464 ( .A(n513), .B(CPU_core_Datapath_ACC[14]), .C(n512), .D(n535), 
        .Q(n514) );
  OAI210 U465 ( .A(n522), .B(CPU_core_Datapath_PC[2]), .C(n521), .Q(n524) );
  NAND20 U466 ( .A(n525), .B(CPU_core_Datapath_Operand[2]), .Q(n523) );
  OAI210 U467 ( .A(n524), .B(n530), .C(n523), .Q(
        CPU_core_Datapath_PC_mux_output[2]) );
  NAND20 U468 ( .A(n525), .B(CPU_core_Datapath_Operand[0]), .Q(n526) );
  OAI210 U469 ( .A(CPU_core_Datapath_PC[0]), .B(n530), .C(n526), .Q(
        CPU_core_Datapath_PC_mux_output[0]) );
  OAI210 U470 ( .A(n528), .B(CPU_core_Datapath_PC[4]), .C(n527), .Q(n531) );
  NAND20 U471 ( .A(n530), .B(CPU_core_Datapath_Operand[4]), .Q(n529) );
  OAI210 U472 ( .A(n531), .B(n530), .C(n529), .Q(
        CPU_core_Datapath_PC_mux_output[4]) );
endmodule