# initialise the database (load in the design)

amsDbSetup


# timing setup

amsSetMMMC
amsSetAnalysisView minmax {func test}


# Place the pad cells (including corners and power) and then snap them to the grid

loadIoFile ../padring/cpu.io
amsUserGrid

# view design in gui

fit


# create some space for the power rings
# 60um spacing is plenty for 2x 20 um power rings

floorPlan -site standard -r 1 0.7 60 60 60 60


# specify the connectivity of for the power nets

amsGlobalConnect both

globalNetConnect gnd! -type pgpin -pin A -inst CORE_GND_* -module {}
globalNetConnect vdd! -type pgpin -pin A -inst CORE_VDD_* -module {}


# add the power rings (note a 20um ring is classed as "wide metal" - >10um)
# spacing of 2um is minimum for thick MET4

addRing \
  -type core_rings \
  -nets {gnd! vdd!} \
  -center 1 \
  -layer {bottom MET3 top MET3 right MET4 left MET4} \
  -width 20 -spacing 2


# add power and ground routing (special route)

sroute \
  -connect { blockPin padPin padRing corePin floatingStripe } \
  -layerChangeRange { MET1 MET4 } \
  -blockPinTarget { nearestTarget } \
  -padPinPortConnect { allPort oneGeom } \
  -padPinTarget { nearestTarget } \
  -corePinTarget { firstAfterRowEnd } \
  -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } \
  -allowJogging 1 \
  -crossoverViaLayerRange { MET1 MET4 } \
  -nets { vdd! gnd! } \
  -allowLayerChange 1 \
  -blockPin useLef \
  -targetViaLayerRange { MET1 MET4 }


# Save intermediate design

saveDesign floorplan.enc
  



# Placement

placeDesign
amsAddEndCaps


# Add Tiehi/Tielo cells

setTieHiLoMode -cell {TIE1 TIE0} -maxFanout 10
addTieHiLo


# Save intermediate design

saveDesign placed.enc




# Pre-CTS Optimisation

setOptMode -fixCap true -fixTran true -fixFanoutLoad false
optDesign -preCTS
optDesign -preCTS -drv


# Clock Tree Synthesis (c.f. Michael Nydegger)
# for small designs with a clock buffering pad there may be few if any clock buffers in the tree


setCTSMode -engine ck

setCTSMode -traceDPinAsLeaf true -traceIOPinAsLeaf true

createClockTreeSpec \
  -bufferList {CLKBU2 CLKBU4 CLKBU6 CLKBU8 CLKBU12 CLKBU15 CLKIN0 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN6 CLKIN8 CLKIN10 CLKIN12 CLKIN15} \
  -routeClkNet -output CONSTRAINTS/clock.clk


# Michael Nydegger does this but I don't think we need to -
# system "sed -i 's/^AutoCTSRootPin.*$/AutoCTSRootPin PAD_Clock\\/Y/' CONSTRAINTS/clock.clk"

specifyClockTree -clkfile CONSTRAINTS/clock.clk

ckSynthesis


# Save intermediate design

saveDesign inc_clock_tree.enc



# Post-CTS - update constraints

set_interactive_constraint_modes {func test}

# replace predicted latency and transition with actual values through clock tree
set_propagated_clock [all_clocks]

# set jitter to 0.5 ns (clock skew is no longer important)

set_clock_uncertainty 0.5 [get_clocks master_clock]

set_analysis_view -setup {func_max func_typ func_min} -hold {func_max func_typ func_min}



# Post-CTS Optimisation

optDesign -postCTS -hold
optDesign -postCTS -drv


# Add filler cells before routing

amsFillperi
amsFillcore

# route with nanoRoute

routeDesign -globalDetail

# Post-route optimisation

setDelayCalMode -engine default -siAware true
setAnalysisMode -analysisType onChipVariation

optDesign -postRoute -hold
optDesign -postRoute
optDesign -postRoute -drv


# Save final design

saveDesign routed.enc