/////////////////////////////////////////////////////////////////////// // // MS5803-02BA Altimeter Sensor module // // this model of the sensor is almost empty // // a more advanced version would respond to SPI commands // and return pressure, temperature and other data // // this module might also be the location of assert statements // to help with debugging // // Ports: // SDO (Output) // Serial Data from Slave to Master // // SDI (Input) // Serial Data from Master to Slave // // SCLK (Input) // SPI Clock pin // // CSB (Input - Active Low) // Chip Select // // /////////////////////////////////////////////////////////////////////// module ms5803_02ba ( output SDO, input SDI, input SCLK, input CSB ); timeunit 1ns; timeprecision 100ps; // the integer variables "pressure" and "temperature" represent values // for environmental parameters // // the values can be set from the testbench and, in a more a more // advanced model of the sensor, they might be used to calculate // values to be returned to the user int pressure = 1013; // pressure in millibars int temperature = 25; // temperature in Celcius // // serial bus timing data based on the MS5803-02BA datasheet // // the datasheet has very little detail but the values // specified here should be both conservative and // easy to achieve in practice // specify specparam tcy = 60ns; // clock cycle SPI clock // this value is intenionally longer than implied // by the 20 MHz maximum clock frequency quoted // on the datasheet specparam tclk1 = 25ns; // SPI clock pulse width HIGH specparam tclk0 = 25ns; // SPI clock pulse width LOW specparam tsucs = 25ns; // chip select setup time specparam thcs = 25ns; // chip select hold time specparam tsud = 25ns; // SDI data setup time specparam thd = 25ns; // SDI data hold time // Serial clock timings $period(posedge SCLK, tcy); $width(posedge SCLK, tclk1); $width(negedge SCLK, tclk0); // Chip Select timings relative to the clock $setup(CSB, posedge SCLK, tsucs); $hold(CSB, posedge SCLK, thcs); // Serial Data timings relative to the clock $setup(SDI, posedge SCLK, tsud); $hold(SDI, posedge SCLK, thd); endspecify endmodule