VLSI Design Project - Preparation for Handin

Implementation of a Simple Design as a Complete IC (Dice Design)

The command required to generate the handin file (handin_dice.tar) is:

    prepare_chip   <dirname>   dice

• behavioural
• gate_level
• constraints
• synthesis
• padring
• place_and_route
• extracted
• post_process

These are the sub-directories that should exist if you follow the design flow suggested by the walkthrough labs. Since these should already exist before you begin the handin preparation, you shouldn't have to move any files in order to get the prepare_chip script to work. If the script warns of missing files it is an indication that the design flow has not been correctly followed. At this stage you should repeat the relevant stage of the design flow rather than trying to resolve the issue of a single missing file.

The Dice Specification Document for 2023/2024 gives details of the requirements for this design. In particular it gives deatils of those aspects of the design which differ from those seen in the semester 1 exercise.

Although the Design Exercise Document for 2023/2024 doesn't specifically mention this submission, it does list these directories along with the expected contents of each.

Main Design Exercise (Milestones and Final Design)

The command required to generate the handin file (handin_xxx.tar) is:

    prepare_chip   [-soc]                <dirname>   initial
    prepare_chip   [-soc]                <dirname>   behavioural
    prepare_chip   [-soc]   [-tsmc180]   <dirname>   gate_level
    prepare_chip   [-soc]   [-tsmc180]   <dirname>   final

• <dirname> is the name of the root directory for the chip design hierarchy.
• -soc indicates that a System-on-Chip design is being submitted
• -tsmc180 indicates that the target process for the design is TSMC 180nm