Full Chip Design Exercise

Aim

Design Style

For this exercise it is required that you design using a semi-custom design style based around a standard cell library provided by the foundry. More advanced designs may also make use of foundry macrocells such as RAMs and ROMs. All designs must be synchronous to the rising edge of a global clock. All designs should have a single active-low reset line to clear all internal flip-flops. All designs should use scan path testability for the isolation of errors following fabrication and to help in the production of test vectors.

It is possible to solve this problem using either with a hardware-only design, or a hardware/software System-on-Chip (SoC) design.

• Hardware-only designs will typically require less initial design effort and will be be smaller (and cheaper) than SoC designs where the overall function is simple.
• Hardware/Software SoC designs can provide a more rapid method of producing more complex functions.

File Location

To avoid problems later in the design process, files should be located as follows:

• SystemVerilog Behavioural Model

      ~/design/chip/behavioural
  

  This directory should contain the SystemVerilog files that make up the behavioural model for your design.

• Software (for SoC designs)

      ~/design/chip/software
  

  This directory will contain the source code (usually written in 'C') and the compiled code (usually in the form of a code.hex or code.vmem file readable by SystemVerilog) for any system-on-chip design which makes use of a compiler/assembler.

  Note that this directory should not exist for non-SoC designs and will probably not be needed for SoC designs based around simple custom designed processors unless they rely on a code.hex/code.vmem file in order to initialise their program memory.

• Testbench files

      ~/design/chip/system
      ~/design/chip/system2
  

  These directories should contain the SystemVerilog files that make up the testbench for your design. The contents of the first of these directories is fixed while the second contains custom designed testbench files.

• Macro Models (optional)

      ~/design/chip/macro_models
  

  This directory should contain the macro model files for designs that include foundry macrocells.

  Note that this directory should not exist for designs that do not make use of foundry macrocells.

• Pad Ring

      ~/design/chip/padring
  

  This directory should contain the pad ring definition files.

• Synthesis Files

      ~/design/chip/synthesis
  

  This directory should contain the hierarchy of files and directories that are created during synthesis with Synopsys Design Compiler.

• Constraints Files

      ~/design/chip/constraints
  

  This directory should contain the constraints files used during synthesis with Synopsys Design Compiler.

• Post-Synthesis Gate-Level Design

      ~/design/chip/gate_level
  

  This directory should contain the post-synthesis gate-level verilog netlist and the associated files required for its simulation.

• Cadence Encounter files

      ~/design/chip/place_and_route
  

  This directory should contain the hierarchy of files and directories that are created during place and route with Cadence Encounter.

• Post-Layout Simulation Files

      ~/design/chip/extracted
  

  This directory should contain the post-layout extracted verilog netlist and the associated files required for its simulation.

• Cadence Virtuoso Files

      ~/design/chip/post_process
  

  This directory should contain the Cadence Virtuoso layout files of the full chip design after abstract replacement and correction of outstanding DRC errors. It should also contain a GDS II file ready for fabrication.

Groups

The design exercise is to be tackled in groups of between three and six. The group may divide the work as it sees fit, but all members of the group should be kept active at all stages of the project.

Deliverables

The deliverables for the project are:

• an initial design document.
• a high level SystemVerilog HDL model of the sports altimeter.
• the chip design itself.
• a user guide for the sports altimeter.
• a technical note for the sports altimeter.
• a suite of tests that demonstrate the functionality of your sports altimeter.
• an individual reflection report from each member of the group.

Further details of these deliverables are (or will be) available on the Web.

Marking