CMOS Gate Array Design Exercise 1999-2000
You are required to write a single group report on the work you have done for this exercise.
You should already have written an interim report on the work carried out last semester. Your new report should contain all the relevant information from the interim report. Your full report should not assume that the reader has access to the interim report.
Remember to include a clear and simple circuit diagram.
Remember to include a diagram which shows all testability inputs and outputs as well as the system inputs and outputs.
Remember to include a completed ULA template with gates and outputs uniquely identified.
Include information on the various circuits constructed as well as the test vectors used.
An updated circuit diagram may help here.
Information too complex for a wafer map may be included in tabular form.
The report should clearly document all of the above, further marks will be available for the quality of the documentation. No marks are available for returning to me, photocopies of documents I provided for you.
Appended to this document there should be a project completion form. It provides a record of your achievements in the laboratory.
You should ensure that this form is completed and signed during the laboratory. The completed form must be appended to your report.
Where a team member does not pull his or her weight, it is possible to flag this problem in the documentation and marks may be adjusted accordingly. Where one team member makes a mistake, the team is responsible for checking the work and correcting or compensating for this mistake.
The report should read as a single document. You should allow time to read the whole document before it is submitted. A high degree of co-ordination is required in order to avoid contradictions and omissions.
Iain McNally
22-2-2000