CMOS Gate Array Design Exercise 1999

Identified processing problems

After some considerable investigation we have been able to identify the cause of low yield problems with this year's CMOS gate arrays.

• Reticle Masks

  For each of the customization stages (contact window and metal), there are two reticle masks which are stepped across the wafer. Each reticle contains the mask information for twelve designs (6 chips):

  Reticle 1

      AB IJ QR
      CD KL ST
  

  Reticle 2

      EF MN UV
      GH OP WX
  

  Because there is only one copy of any one design on the reticle, a reticle fault will show up as a systematic failure on all copies of the design on all wafers.

• Suspected Problem with Reticle 2

  Initial testing showed a much better yield for design T than design X both being identical shaft encoder interface designs created for a previous D2. Additionally it was discovered that design S yield was better than that for design V with both being much better than design W - all three are identical copies of the simple sequencer designed by students in the introductory Icebox sessions.

  Some sort of reticle problem was suspected since the yields do not normally vary significantly for different chips and since all poor performing designs were on reticle 2. It was not possible to identify a particular systematic fault since all designs were found to work somewhere (with yields as low as 2 sites in 60 for design W).

  On the basis of this suspicion a new batch of wafers were ordered with new reticles. These were the gold wafers which some of you met during testing. Unfortunately the new wafers seemed to suffer the same yield problems as the original batch leaving us none the wiser.

  During student testing it was confirmed that teams with designs on reticle 2 (E,F,G,H,M,N,O & P) received lower yields than those with designs on reticle 1.

• Actual Problem with Reticle 2

  The actual problem with reticle 2 was eventually identified to be a combination of three factors:

  1. The original reticle had strands of etch resist left on the reticle after cleaning. These strands can be seen in the left hand micrographs of the reticle. The effect on the metal laid down can be judged from the right hand (back lit) micrographs where the black areas will become metal tracks.
     

  2. The next problem is due to improvements in the cleanrooms. Because of requirements to produce sub-micron designs, our process is capable of creating metal tracks of such small size as were defined by the etch resist strands (very much smaller than the 4 micron minimum metal width suggested by the standard design rules). These tracks cause shorts on the final chips leading to high static current consumption and chip failure. They are not immediately identifiable as systematic faults since over-etching of metal around the edge of the wafer removes these very thin strands of metal allowing some chips to function.

  3. The last problem was simple human error. The gold wafers were supposed to get a different copy of reticle 2 but instead they ended up with the old faulty reticle leaving us confused as to how a new reticle might exhibit the same problems as the first.

  These problems were eventually identified during extensive post-mortem investigations carried out over the Easter break.

Overall we have learnt a lot from the problems experienced this year. In general the teams coped well with the yield problems, extracting as much information from the wafers as was possible. I hope that this document will help to provide the explanations which were not available during the testing exercise.