CMOS Gate Array Design Exercise 2001-2002

• Testing documentation

  The final versions of these documents are available on the web. The paper copies (one per team) may be picked up from Zepler reception anytime after 15/04/2002.

• Simulation

  Simulation is an important part of any IC design. A number of different simulation files have been created to allow you to simulate your full circuit or one of the sub-modules. You should ensure that you are familiar with the web document: Using Simulation as part of a Modular Design Strategy in order to get most benefit from the simulation options available.

  Currently the following simulation options are supported:

  • test : for the test circuit
  • final : for the full mouse circuit
  • any : a vanilla simulation for customization

  • updown : for the updown unit only
  • button : for the button unit only
  • counter : for a counter with 4 or more bits (won't work with updown attached)
  • counter3 : for a counter with only 3 bits (won't work with updown attached)
  • counter2 : for a counter with only 2 bits (won't work with updown attached)
  • all : for the full mouse circuit with a four+ bit counter
  • all3 : for the full mouse circuit with a three bit counter
  • all2 : for the full mouse circuit with a two bit counter
  
  

• Layout vs Schematic Checking (LVS)

  LVS is now available.

  • LVS can be a major help to designers working on layout. It can be used before or after simulation. If used before simulation it can provide much faster identification of problems than other methods.

  • An LVS check will be performed on every submitted design - this check will be used to help in the marking process.

  • There are two ways for you to run LVS
    1. Schematic Netlist ...then... Layout LVS
       Make sure you have netlisted an up to date copy of the schematic from your account before attempting to run an LVS on the layout.
    2. Layout Netlist ...then... Schematic LVS
       Make sure you have netlisted an up to date copy of the layout from your account before attempting to run an LVS on the schematic.

  • LVS will only work if the schematic matches the layout exactly - including the test RS flip flop present on all designs.
    The RS should look like this:

  • LVS occasionally complains that there are errors in the correspondence file. This happens if not all the pin names on the schematic exist on the layout.

• Missing Waves Window

  With current installations of Windows 2000 and Exceed the Waves window displayed by Exceed pops up behind the icebox window.

  Simply select Waves icon from the icon bar to bring it into view.