CMOS Gate Array Design Exercise 2001
14:00 Thursday 11th October in Shackleton Lecture Theatre A
Monday 22nd October in ECAD laboratory.
Teams A, B, C, D, E, F, G & H should attend 09:55 - 12:40
Teams I, J, K, L, M, N & O should attend 13:50 - 16:35
Monday 29th October in ECAD laboratory.
Teams A, B, C, D, E, F, G & H should attend 09:55 - 12:40
Teams I, J, K, L, M, N & O should attend 13:50 - 16:35
Friday 2nd November
Designs should be submitted electronically via the Remote CAD tools facility.
Interim reports should be submitted to the Zepler Coursework office by 16:00.
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Iain McNally
4-10-2001