CMOS Gate Array Design Exercise 2000-2001

• Testing documentation

  The final versions of these documents is available on the web. The paper copies (one per team) may be picked up from Chris Harris in Stores from Monday.

• More stringent simulation

  The "simulate_final" code now does some more tests in order to check more of the specification.

• Use of VDD and GND cells

  Some teams may have to use the VDD or GND cells to tie signals within there designs. For instance if you support all the modes then the Unsupported signal can be driven from VDD via an inverter (note that connecting it directly to GND would cause a name clash).

  A bug which prevented the simulation of schematics using VDD/GND has been identified and corrected. Note that the VDD/GND cells are ignored by LVS so if you make a mistake with them LVS won't tell you - use these cells with caution.

• Down Counter Simulation

  You can simulate a programmable down counter module by selection "-simulate downcount" in place of "-simulate test" or "-simulate final" or "-simulate any". The simulation will work if the inputs to the counter are named : CLOCK, nRESET, Mode0, Mode1 & Trigger. Note that no pass/fail result is given this will be up to you to decide.

• Signed Numbers

  There appears to be some confusion over the Signed input to the multiply unit controller. If the Signed input is asserted (high) it indicates that both A and B are 2's complement signed numbers. If the Signed input is not asserted then both A and B are unsigned.

  Note that the input does not tell us if the numbers are negative only that they are signed, for 2's complement numbers a negative value is indicated by a '1' in the most signifcant bit position. (c.f. +5 -6 -12 +3 are all signed decimal numbers but you must check the sign to see if the number is negative)

• Plotting from Icebox

  Plotting from Icebox now works although currently only in black and white (sufficient for the interim report).

  I plotted from the ECAD lab to Snowdon in the main lab since there are apparently still problems with printing to Goudy (unrelated to Icebox).

• Layout vs Schematic Checking (LVS)

  LVS is now available.

  • LVS can be a major help to designers working on layout. It can be used before or after simulation. If used before simulation it can provide much faster identification of problems than other methods.

  • An LVS check will be performed on every submitted design - this check will be used to help in the marking process.

  • There are two ways for you to run LVS
    1. Schematic Netlist ...then... Layout LVS
       Make sure you have netlisted an up to date copy of the schematic from your account before attempting to run an LVS on the layout.
    2. Layout Netlist ...then... Schematic LVS
       Make sure you have netlisted an up to date copy of the layout from your account before attempting to run an LVS on the schematic.

  • LVS will only work if the schematic matches the layout exactly - including the test RS flip flop present on all designs.
    The RS should look like this:

  • LVS occasionally complains that there are errors in the correspondence file. This happens if not all the pin names on the schematic exist on the layout.

• Missing Waves Window

  With current installations of Windows 2000 and Exceed the Waves window displayed by Exceed pops up behind the icebox window.

  Simply select Waves icon from the icon bar to bring it into view.

• Introductory Meeting

  The Introductory meeting will take place on Thursday 19^th October at 14:00 in Law lecture theatre A.

  (This lecture theatre is in the middle of the Nuffield Foyer)

  All students doing D2 this year must attend.