CMOS Gate Array Design Exercise 2000

Initial Submission Feedback


Simulation Results

Simple Simulation

On submission, the designs were simulated again with the simple stimulus used in the simulate_final turnkey simulation.

All designs passed the simple simulations with the exception of:
 
Team A Attempts multiplication when in unsupported modes.
Team F Provides no Unsupported signal
Team O Doesn't recover from dealing with -ve numbers

Advanced Simulation

New verilog stimulus files where written to test operation in more detail. These simulations turned up some interesting results:
 
Mode = 0 Mode = 1 Mode = 2 Mode = 3
Team A 8 bit 16 bit fails fails
Team B 7 bit 15 bit 31 bit Unsupported
Team C 9 bit 17 bit 25 bit fails
Team D 7 bit 15 bit 31 bit Unsupported
Team E 7 bit (unsigned only) 15 bit (unsigned only) 31 bit (unsigned only) Unsupported
Team F 8 bit fails fails n bit (signed only)
Team G 8 bit 16 bit 32 bit Unsupported
Team H 8 bit (signed only) 16 bit (signed only) 32 bit (signed only) Unsupported
Team I 8 bit 16 bit Unsupported Unsupported
Team L 8 bit 16 bit 32 bit n bit (signed only)
Team M 8 bit 16 bit 32 bit n bit
Team N 8 bit 16 bit 32 bit n bit
Team O 8 bit (unsigned only) Unsupported Unsupported Unsupported

The most common fault is in the timing of multiplications, with three teams implementing multiplications with one too few cycles (e.g. 7 bit multiplication where 8 bit multiplication was required) and one team with one too many cycles. These problems and problems with signed/unsigned numbers should be relatively easy to cope with during the testing exercise next semester.

The most serious problems are with state machines that continue to operate in some way after a multiplication is complete. This is the cause of the failed modes for Team F and Team O.
 

Fabrication

Your designs have now been merged with a number test designs to produce two reticle masks each containing 12 ICs on 6 chips. Following mask making, the masks will be used to customize wafers to your specifications. Customized wafers will be ready for you to test next semester.
 

Conclusions

Overall the teams have done well with no team unable to demonstrate functionality of at least one mode. Together with proven correspondence between layout and schematic, as indicated by good LVS results, this should help the testing exercise next semester to run more smoothly.

Iain McNally
Revision B
27-11-2000