CMOS Gate Array Design Exercise
The following documents are available:
Designing for the CMOS Gate Array 2002/2003
Designing for the CMOS Gate Array
Use of Icebox for CMOS Gate Array design
(additional information)
Forms:
CGA Placement Template(pdf)
Design Submission Form(pdf)
Sample Interim Report
Icebox Documentation
Simulation
Using Simulation as part of a Modular Design Strategy
Verilog XL documentation
Simulation of OrCAD designs using Verilog
01-02
STOP PRESS
Introductory Meeting 2001
- Thursday 11th October
Schedule 2001
Supervised Introductory Icebox Sessions
- Monday 22nd October
Design Specification 2001 - PS/2 Mouse Interface
Initial Submission Details 2001
Testing 2002 - PS/2 Mouse Interface
Wafer Map
Final Submission Details 2002
Notes on D2 reports 1999-2000
D2 Project Completion Form
00-01
STOP PRESS
Introductory Meeting 2000
Schedule 2000
Supervised Introductory Icebox Sessions
Design Specification 2000 - Versatile Multiply Unit Controller
Initial Submission Details 2000
Initial Submission Feedback - November 2000
Testing 2001 - Versatile Multiply Unit Controller
Wafer Map
Final Submission Details 2001
D2 Project Completion Form
99-00
Design Specification 1999 - Frame Synchronization Unit
Testing 2000 - Frame Synchronization Unit
Final Submission Details 2000
Wafer Map
Tasks for Test Circuit Building Team
Identified processing problems
Notes on D2 reports 1999-2000
98-99
Design Specification 1998 - Hamming Encoder/Decoder
97-98
Design Specification - Serial Mouse
CMOS ULA - Testing - Serial Mouse
96-97
Design Specification - ADC controller
CMOS ULA - Testing - ADC controller