#----------------------------------------------------------- # Vivado v2013.4 (64-bit) # SW Build 353583 on Mon Dec 9 17:49:19 MST 2013 # IP Build 208076 on Mon Dec 2 12:38:17 MST 2013 # Start of session at: Sun Apr 13 13:53:06 2014 # Process ID: 8236 # Log file: C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/vivado.log # Journal file: C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4\vivado.jou #----------------------------------------------------------- Attempting to get a license: Implementation WARNING: [Common 17-301] Failed to get a license: Implementation WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation. Attempting to get a license: Synthesis WARNING: [Common 17-301] Failed to get a license: Synthesis Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] start_gui open_project {C:\Users\karshi01\Desktop\Workshop\USB\Full Material - V5\Solutions\P8\lab\FPGA\nexys4\nexys4.xpr} INFO: [Project 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4' INFO: [Project 1-313] Project file moved from 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V3/P8/lab/FPGA/nexys4' since last save. Scanning sources... Finished scanning sources reset_run impl_1 launch_runs impl_1 ERROR: [Runs 36-50] cannot prep a run with an unknown status launch_runs impl_1 ERROR: [Runs 36-50] cannot prep a run with an unknown status reset_run synth_1 launch_runs synth_1 [Sun Apr 13 13:53:36 2014] Launched synth_1... Run output will be captured here: C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/nexys4.runs/synth_1/runme.log launch_runs impl_1 [Sun Apr 13 13:55:53 2014] Launched impl_1... Run output will be captured here: C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/nexys4.runs/impl_1/runme.log launch_runs impl_1 -to_step write_bitstream [Sun Apr 13 13:57:33 2014] Launched impl_1... Run output will be captured here: C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/nexys4.runs/impl_1/runme.log open_hw connect_hw_server -host localhost -port 60001 INFO: [Xicom 50-2] Connecting to hw_server... INFO: [Xicom 50-1] Attempting to launch hw_server... INFO: [#UNDEF] ****** Xilinx hw_server v2013.4 **** Build date : Dec 9 2013-17:47:52 ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. INFO: hw_server application started INFO: Use Ctrl-C to exit hw_server application INFO: [Labtools 27-109] Started Vivado Cse Server instance on port: 60001 INFO: [Labtools 27-147] vcse_server: Connecting to hw_server... INFO: [Labtools 27-147] vcse_server: Connection established. INFO: [Labtools 27-147] vcse_server: Connecting to hw_server... INFO: [Labtools 27-147] vcse_server: Connection established. connect_hw_server: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 905.563 ; gain = 5.262 current_hw_target [get_hw_targets */xilinx_tcf/Digilent/210274533378A] open_hw_target INFO: [Labtools 27-147] vcse_server: Connecting to hw_server... INFO: [Labtools 27-147] vcse_server: Connection established. set_property PROGRAM.FILE {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/nexys4.runs/impl_1/AHBLITE_SYS.bit} [lindex [get_hw_devices] 0] set_property PROBES.FILE {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/nexys4.runs/impl_1/debug_nets.ltx} [lindex [get_hw_devices] 0] current_hw_device [lindex [get_hw_devices] 0] refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. set_property PROGRAM.FILE {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Tools/download_19200.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-2154] Reading 3825873 bytes from file C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Tools/download_19200.bit... INFO: [Labtools 27-32] Done pin status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. set_property PROGRAM.FILE {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/nexys4.runs/impl_1/AHBLITE_SYS.bit} [lindex [get_hw_devices] 0] program_hw_devices [lindex [get_hw_devices] 0] INFO: [Labtools 27-2154] Reading 3825881 bytes from file C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P8/lab/FPGA/nexys4/nexys4.runs/impl_1/AHBLITE_SYS.bit... INFO: [Labtools 27-32] Done pin status: HIGH refresh_hw_device [lindex [get_hw_devices] 0] INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. exit INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 14:00:57 2014...