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53*	vivadotcl2 
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308*common2"
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310*common2"
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xc7a100t2default:defaultZ17-349
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22*	vivadotcl2 
place_design2default:defaultZ4-22
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24*drc2

22default:defaultZ23-27
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79*	vivadotcl2
0 Errors2default:defaultZ4-198
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BPlease refer to the DRC report (report_drc) for more information.
80*	vivadotclZ4-199
L

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103*constraints2
Placer2default:defaultZ18-103
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BMultithreading enabled for place_design using a maximum of %s CPUs12*	placeflow2

22default:defaultZ30-611
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101*constraints2
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101*constraints2
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02default:defaultZ31-140
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98*opt2

02default:defaultZ31-138
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891.7112default:default2
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101*constraints2
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101*constraints2
1.1.3 2default:default2#
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101*constraints2
1.1.4 2default:default2 
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101*constraints2
1.1.5 2default:default24
 Implementation Feasibility check2default:defaultZ18-101
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ZTime (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 891.711 ; gain = 0.0002default:default
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101*constraints2
1.1.6 2default:default2#
Pre-Place Cells2default:defaultZ18-101
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1Phase 1.1.6 Pre-Place Cells | Checksum: b05a0d00
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101*constraints2
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ZTime (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 894.059 ; gain = 2.3482default:default
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Phase %s%s
101*constraints2
1.1.8 2default:default2.
Build Placer Netlist Model2default:defaultZ18-101
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Phase %s%s
101*constraints2
1.1.8.1 2default:default2%
Place Init Design2default:defaultZ18-101
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101*constraints2

1.1.8.1.1 2default:default2$
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6Phase 1.1.8.1.1 Build Clock Data | Checksum: e88bfe33
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6Phase 1.1.8.1 Place Init Design | Checksum: 19fcb50aa
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101*constraints2
1.1.9 2default:default2+
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101*constraints2
1.1.9.1 2default:default24
 Constrain Global/Regional Clocks2default:defaultZ18-101
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EPhase 1.1.9.1 Constrain Global/Regional Clocks | Checksum: 19fcb50aa
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101*constraints2
2 2default:default2$
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101*constraints2
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101*constraints2
3 2default:default2$
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101*constraints2
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101*constraints2
3.2 2default:default20
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[Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 916.074 ; gain = 24.3632default:default
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101*constraints2
3.3 2default:default2*
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7Phase 3.3 Area Swap Optimization | Checksum: 18eb56952
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101*constraints2
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6Phase 3.4 Timing Path Optimizer | Checksum: 19f4b84da
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101*constraints2
3.5 2default:default24
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APhase 3.5 Commit Small Macros & Core Logic | Checksum: 14b51cf71
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101*constraints2
3.6 2default:default2&
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3Phase 3.6 Re-assign LUT pins | Checksum: 14b51cf71
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101*constraints2
4 2default:default2<
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101*constraints2
4.1 2default:default2'
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4Phase 4.1 PCOPT Shape updates | Checksum: 1e4d34eac
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101*constraints2
4.2 2default:default2/
Post Placement Optimization2default:defaultZ18-101
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101*constraints2
4.2.1 2default:default26
"Post Placement Timing Optimization2default:defaultZ18-101
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[Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 938.598 ; gain = 46.8872default:default
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101*constraints2
4.3 2default:default2*
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7Phase 4.3 Post Placement Cleanup | Checksum: 1fbaf5457
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101*constraints2
4.4 2default:default2$
Placer Reporting2default:defaultZ18-101
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101*constraints2
4.4.1 2default:default2(
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7Phase 4.4.1 Congestion Reporting | Checksum: 1fbaf5457
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101*constraints2
4.4.2 2default:default2&
updateTiming final2default:defaultZ18-101
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5Phase 4.4.2 updateTiming final | Checksum: 1a0a91cdb
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[Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 938.598 ; gain = 46.8872default:default
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101*constraints2
4.4.3 2default:default2(
Dump Critical Paths 2default:defaultZ18-101
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7Phase 4.4.3 Dump Critical Paths  | Checksum: 1a0a91cdb
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101*constraints2
4.4.4 2default:default2
Restore STA2default:defaultZ18-101
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[Time (s): cpu = 00:00:37 ; elapsed = 00:00:32 . Memory (MB): peak = 938.598 ; gain = 46.8872default:default
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101*constraints2
4.4.5 2default:default2#
Print Final WNS2default:defaultZ18-101
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2*	placeflow20
| WNS=8.882  | TNS=0.000  |
2default:defaultZ30-100
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101*constraints2
4.5 2default:default2+
Final Placement Cleanup2default:defaultZ18-101
D
8Phase 4.5 Final Placement Cleanup | Checksum: 1dbd0c9a1
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GPhase 4 Post Placement Optimization and Clean-Up | Checksum: 1dbd0c9a1
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[Time (s): cpu = 00:00:44 ; elapsed = 00:00:38 . Memory (MB): peak = 940.852 ; gain = 49.1412default:default
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%s
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[Time (s): cpu = 00:00:00 ; elapsed = 00:00:38 . Memory (MB): peak = 940.852 ; gain = 49.1412default:default
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83*common2"
Implementation2default:defaultZ17-83
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G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
322default:default2

02default:default2

02default:default2

02default:defaultZ4-41
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%s completed successfully
29*	vivadotcl2 
place_design2default:defaultZ4-42
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I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
place_design: 2default:default2
00:00:452default:default2
00:00:382default:default2
940.8522default:default2
51.0272default:defaultZ17-268
^

DEBUG : %s144*timing29
%Generate clock report | CPU: 0 secs 
2default:defaultZ38-163

sreport_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.168 . Memory (MB): peak = 940.852 ; gain = 0.000
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DEBUG : %s134*designutils2@
,Generate Control Sets report | CPU: 0 secs 
2default:defaultZ20-134
4
Writing XDEF routing.
211*designutilsZ20-211
A
#Writing XDEF routing logical nets.
209*designutilsZ20-209
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#Writing XDEF routing special nets.
210*designutilsZ20-210
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268*common2)
Write XDEF Complete: 2default:default2
00:00:012default:default2
00:00:012default:default2
940.8522default:default2
0.0002default:defaultZ17-268


End Record