*** Running vivado with args -log AHBLITE_SYS.rds -m64 -mode batch -messageDb vivado.pb -source AHBLITE_SYS.tcl ****** Vivado v2013.4 (64-bit) **** SW Build 353583 on Mon Dec 9 17:49:19 MST 2013 **** IP Build 208076 on Mon Dec 2 12:38:17 MST 2013 ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. Attempting to get a license: Implementation WARNING: [Common 17-301] Failed to get a license: Implementation WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation. Attempting to get a license: Synthesis WARNING: [Common 17-301] Failed to get a license: Synthesis Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] source AHBLITE_SYS.tcl # set_param gui.test TreeTableDev # set_msg_config -id {HDL 9-1061} -limit 100000 # set_msg_config -id {HDL 9-1654} -limit 100000 # create_project -in_memory -part xc7a100tcsg324-1 # set_property target_language Verilog [current_project] # set_param project.compositeFile.enableAutoGeneration 0 # read_verilog { # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/CortexM0-DS/cortexm0ds_logic.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/uart_tx.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/uart_rx.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/fifo.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/baudgen.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/CortexM0-DS/CORTEXM0DS.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/AHBUART.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_SRAM/AHB2SRAMFLSH.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_LED/AHB2LED.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_BUS/AHBMUX.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_BUS/AHBDCD.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v} # } # read_xdc {{C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/Nexys4_Master.xdc}} INFO: [Project 1-11] Changing the constrs_type of fileset 'constrs_1' to 'XDC'. # set_property used_in_implementation false [get_files {{C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/Nexys4_Master.xdc}}] # set_param synth.vivado.isSynthRun true # set_property webtalk.parent_dir {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.data/wt} [current_project] # set_property parent.project_dir {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4} [current_project] # synth_design -top AHBLITE_SYS -part xc7a100tcsg324-1 Command: synth_design -top AHBLITE_SYS -part xc7a100tcsg324-1 Starting synthesis... Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' WARNING: [Synth 8-2611] redeclaration of ansi port LOCKUP is not allowed [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:101] WARNING: [Synth 8-976] LOCKUP has already been declared [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:101] WARNING: [Synth 8-2654] second declaration of LOCKUP ignored [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:101] INFO: [Synth 8-994] LOCKUP is declared here [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:45] --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 246.547 ; gain = 100.395 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'AHBLITE_SYS' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:38] INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:612] INFO: [Synth 8-256] done synthesizing module 'BUFG' (1#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:612] INFO: [Synth 8-638] synthesizing module 'CORTEXM0DS' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/CortexM0-DS/CORTEXM0DS.v:27] INFO: [Synth 8-638] synthesizing module 'cortexm0ds_logic' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/CortexM0-DS/cortexm0ds_logic.v:27] INFO: [Synth 8-256] done synthesizing module 'cortexm0ds_logic' (2#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/CortexM0-DS/cortexm0ds_logic.v:27] INFO: [Synth 8-256] done synthesizing module 'CORTEXM0DS' (3#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/CortexM0-DS/CORTEXM0DS.v:27] INFO: [Synth 8-638] synthesizing module 'AHBDCD' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_BUS/AHBDCD.v:38] INFO: [Synth 8-256] done synthesizing module 'AHBDCD' (4#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_BUS/AHBDCD.v:38] INFO: [Synth 8-638] synthesizing module 'AHBMUX' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_BUS/AHBMUX.v:38] INFO: [Synth 8-256] done synthesizing module 'AHBMUX' (5#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_BUS/AHBMUX.v:38] INFO: [Synth 8-638] synthesizing module 'AHB2SRAMFLSH' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_SRAM/AHB2SRAMFLSH.v:38] Parameter idle bound to: 16'b0000000000000000 Parameter read1 bound to: 16'b0000000000000001 Parameter read2 bound to: 16'b0000000000000010 Parameter read3 bound to: 16'b0000000000000100 Parameter read4 bound to: 16'b0000000000001000 Parameter write1 bound to: 16'b0000000100000000 Parameter write2 bound to: 16'b0000001000000000 Parameter write3 bound to: 16'b0000010000000000 Parameter write4 bound to: 16'b0000100000000000 Parameter write5 bound to: 16'b0001000000000000 Parameter write6 bound to: 16'b0010000000000000 INFO: [Synth 8-256] done synthesizing module 'AHB2SRAMFLSH' (6#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_SRAM/AHB2SRAMFLSH.v:38] WARNING: [Synth 8-350] instance 'uAHB2SRAMFLSH' of module 'AHB2SRAMFLSH' requires 25 connections, but only 22 given [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:225] INFO: [Synth 8-638] synthesizing module 'AHBUART' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/AHBUART.v:38] INFO: [Synth 8-638] synthesizing module 'BAUDGEN' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/baudgen.v:37] INFO: [Synth 8-256] done synthesizing module 'BAUDGEN' (7#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/baudgen.v:37] INFO: [Synth 8-638] synthesizing module 'FIFO' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/fifo.v:38] Parameter DWIDTH bound to: 8 - type: integer Parameter AWIDTH bound to: 4 - type: integer INFO: [Synth 8-155] case statement is not full and has no default [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/fifo.v:115] INFO: [Synth 8-256] done synthesizing module 'FIFO' (8#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/fifo.v:38] INFO: [Synth 8-638] synthesizing module 'UART_RX' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/uart_rx.v:38] Parameter idle_st bound to: 2'b00 Parameter start_st bound to: 2'b01 Parameter data_st bound to: 2'b11 Parameter stop_st bound to: 2'b10 INFO: [Synth 8-256] done synthesizing module 'UART_RX' (9#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/uart_rx.v:38] INFO: [Synth 8-638] synthesizing module 'UART_TX' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/uart_tx.v:38] Parameter idle_st bound to: 2'b00 Parameter start_st bound to: 2'b01 Parameter data_st bound to: 2'b11 Parameter stop_st bound to: 2'b10 INFO: [Synth 8-256] done synthesizing module 'UART_TX' (10#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/uart_tx.v:38] INFO: [Synth 8-256] done synthesizing module 'AHBUART' (11#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/AHBUART.v:38] WARNING: [Synth 8-350] instance 'uAHBUART' of module 'AHBUART' requires 13 connections, but only 12 given [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:252] INFO: [Synth 8-638] synthesizing module 'AHB2LED' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_LED/AHB2LED.v:1] INFO: [Synth 8-256] done synthesizing module 'AHB2LED' (12#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_LED/AHB2LED.v:1] INFO: [Synth 8-256] done synthesizing module 'AHBLITE_SYS' (13#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:38] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 437.867 ; gain = 291.715 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[27] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[26] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[25] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[24] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[23] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[22] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[21] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[20] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[19] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[18] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[17] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[16] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[15] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[14] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[13] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[12] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[11] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[10] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[9] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[8] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[7] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[6] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[5] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[4] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[3] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[2] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[1] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[0] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[27] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[26] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[25] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[24] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[23] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[22] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[21] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[20] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[19] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[18] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[17] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[16] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[15] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[14] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[13] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[12] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[11] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[10] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[9] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[8] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[7] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[6] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[5] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[4] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[3] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[2] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[1] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[0] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[27] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[26] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[25] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[24] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[23] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[22] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[21] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[20] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[19] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[18] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[17] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[16] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[15] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[14] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[13] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[12] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[11] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[10] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[9] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[8] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[7] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[6] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[5] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[4] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[3] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[2] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[1] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[0] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S6[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S6[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S6[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S6[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHBLITE_SYS.v:190] INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml... Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml Loading device configuration modes from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml Processing XDC Constraints Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/Nexys4_Master.xdc] Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/Nexys4_Master.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/synth_1/.Xil/AHBLITE_SYS_propImpl.xdc]. Resolution: To avoid this message, exclude constraints listed in [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/synth_1/.Xil/AHBLITE_SYS_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 619.977 ; gain = 473.824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 619.977 ; gain = 473.824 --------------------------------------------------------------------------------- WARNING: [Synth 8-3936] Found unconnected internal register 'last_HADDR_reg' and it is trimmed from '32' to '8' bits. [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/AHB_UART/AHBUART.v:104] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:57 ; elapsed = 00:00:59 . Memory (MB): peak = 619.977 ; gain = 473.824 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 34 Bit Adders := 2 2 Input 31 Bit Adders := 1 2 Input 30 Bit Adders := 1 2 Input 24 Bit Adders := 1 2 Input 22 Bit Adders := 1 2 Input 9 Bit Adders := 1 2 Input 4 Bit Adders := 11 2 Input 3 Bit Adders := 2 +---XORs : 2 Input 1 Bit XORs := 59 +---Registers : 32 Bit Registers := 2 22 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 4 4 Bit Registers := 8 3 Bit Registers := 3 2 Bit Registers := 4 1 Bit Registers := 851 +---RAMs : 128 Bit RAMs := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 22 Bit Muxes := 5 2 Input 16 Bit Muxes := 2 11 Input 16 Bit Muxes := 1 2 Input 12 Bit Muxes := 2 10 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 3 2 Input 10 Bit Muxes := 1 2 Input 8 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 3 10 Input 4 Bit Muxes := 1 6 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 4 Input 3 Bit Muxes := 2 4 Input 2 Bit Muxes := 2 2 Input 2 Bit Muxes := 3 11 Input 1 Bit Muxes := 1 4 Input 1 Bit Muxes := 23 2 Input 1 Bit Muxes := 406 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module AHBLITE_SYS Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module cortexm0ds_logic Detailed RTL Component Info : +---Adders : 2 Input 34 Bit Adders := 2 2 Input 31 Bit Adders := 1 2 Input 30 Bit Adders := 1 2 Input 24 Bit Adders := 1 2 Input 9 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 59 +---Registers : 1 Bit Registers := 839 +---Muxes : 2 Input 1 Bit Muxes := 386 Module CORTEXM0DS Detailed RTL Component Info : Module AHBDCD Detailed RTL Component Info : +---Muxes : 11 Input 16 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 Module AHBMUX Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 11 Input 1 Bit Muxes := 1 Module AHB2SRAMFLSH Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 +---Registers : 32 Bit Registers := 2 16 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 32 Bit Muxes := 1 2 Input 22 Bit Muxes := 4 2 Input 16 Bit Muxes := 2 2 Input 12 Bit Muxes := 2 10 Input 12 Bit Muxes := 1 2 Input 11 Bit Muxes := 3 2 Input 10 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 10 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 4 Module BAUDGEN Detailed RTL Component Info : +---Adders : 2 Input 22 Bit Adders := 1 +---Registers : 22 Bit Registers := 1 +---Muxes : 2 Input 22 Bit Muxes := 1 2 Input 1 Bit Muxes := 2 Module FIFO Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 4 +---Registers : 4 Bit Registers := 2 1 Bit Registers := 2 +---RAMs : 128 Bit RAMs := 1 +---Muxes : 4 Input 1 Bit Muxes := 6 Module UART_RX Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 2 Bit Registers := 1 +---Muxes : 6 Input 4 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 4 Input 1 Bit Muxes := 5 2 Input 1 Bit Muxes := 7 Module UART_TX Detailed RTL Component Info : +---Adders : 2 Input 4 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---Registers : 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 4 Bit Muxes := 1 4 Input 3 Bit Muxes := 1 4 Input 2 Bit Muxes := 1 2 Input 2 Bit Muxes := 1 4 Input 1 Bit Muxes := 6 2 Input 1 Bit Muxes := 6 Module AHBUART Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module AHB2LED Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[31] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[30] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[29] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[28] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[27] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[26] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[25] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[24] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HSIZE_reg[2] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHBUART/last_HTRANS_reg[0] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2LED/rHTRANS_reg[0] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[31] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[30] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[29] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[28] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[27] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[26] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[25] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HADDR_reg[24] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/APhase_HSIZE_reg[2] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHBUART/last_HTRANS_reg[0] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2LED/rHTRANS_reg[0] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3917] design AHBLITE_SYS has port MemAdr[23] driven by constant 0 WARNING: [Synth 8-3917] design AHBLITE_SYS has port RamCRE driven by constant 0 WARNING: [Synth 8-3917] design AHBLITE_SYS has port RamADVn driven by constant 0 WARNING: [Synth 8-3917] design AHBLITE_SYS has port RamCLK driven by constant 0 WARNING: [Synth 8-3331] design AHBLITE_SYS has unconnected port RamWait --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:58 ; elapsed = 00:01:01 . Memory (MB): peak = 628.484 ; gain = 482.332 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: +------------+---------------------------------+--------------------+----------------------+--------------+--------------------+ |Module Name | RTL Object | Inference Criteria | Size (depth X width) | Primitives | Hierarchical Name | +------------+---------------------------------+--------------------+----------------------+--------------+--------------------+ |AHBLITE_SYS | uAHBUART/uFIFO_TX/array_reg_reg | Implied | 16 X 8 | RAM32M x 2 | AHBLITE_SYS/ram__2 | |AHBLITE_SYS | uAHBUART/uFIFO_RX/array_reg_reg | Implied | 16 X 8 | RAM32M x 2 | AHBLITE_SYS/ram__3 | +------------+---------------------------------+--------------------+----------------------+--------------+--------------------+ Note: Mutiple instantiated RAMs are reported only once. "Hierarchical Name" reflects the hierarchical modules names of the RAM and only part of it is displayed. --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3333] propagating constant 0 across sequential element (\u_cortexm0ds/u_logic /Qnn2z4_reg) INFO: [Synth 8-3333] propagating constant 0 across sequential element (\uAHB2SRAMFLSH/pstate_reg[4] ) WARNING: [Synth 8-3332] Sequential element (Ypi3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Aii3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Q0f3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Mvi2z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (I6h3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Q4h3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (W8r2z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Jje3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Etq2z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (C7f3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Gzb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (O2c3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Rnb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (W5c3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Qsb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (E9c3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Zqb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Yvb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Qnn2z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[15] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[14] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[13] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[12] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[7] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[6] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[5] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2SRAMFLSH/pstate_reg[4] ) is unused and will be removed from module AHBLITE_SYS. --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:01:35 ; elapsed = 00:01:38 . Memory (MB): peak = 771.191 ; gain = 625.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:36 ; elapsed = 00:01:38 . Memory (MB): peak = 771.191 ; gain = 625.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:36 ; elapsed = 00:01:39 . Memory (MB): peak = 771.191 ; gain = 625.039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\uAHB2LED/rHWRITE_reg ) is unused and will be removed from module AHBLITE_SYS. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:50 ; elapsed = 00:01:54 . Memory (MB): peak = 844.781 ; gain = 698.629 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Gated Clock Conversion mode: off --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:51 ; elapsed = 00:01:55 . Memory (MB): peak = 846.895 ; gain = 700.742 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:51 ; elapsed = 00:01:55 . Memory (MB): peak = 846.895 ; gain = 700.742 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:51 ; elapsed = 00:01:55 . Memory (MB): peak = 846.895 ; gain = 700.742 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 2| |2 |CARRY4 | 46| |3 |INV | 16| |4 |LUT1 | 127| |5 |LUT2 | 326| |6 |LUT3 | 251| |7 |LUT4 | 404| |8 |LUT5 | 573| |9 |LUT6 | 1945| |10 |MUXF7 | 9| |11 |RAM32M | 4| |12 |FDCE | 275| |13 |FDPE | 710| |14 |FDRE | 12| |15 |IBUF | 3| |16 |IOBUF | 16| |17 |OBUF | 41| +------+-------+------+ Report Instance Areas: +------+----------------+-----------------+------+ | |Instance |Module |Cells | +------+----------------+-----------------+------+ |1 |top | | 4760| |2 | uAHB2SRAMFLSH |AHB2SRAMFLSH | 149| |3 | u_cortexm0ds |CORTEXM0DS | 4226| |4 | u_logic |cortexm0ds_logic | 4215| |5 | uAHBMUX |AHBMUX | 71| |6 | uAHBUART |AHBUART | 217| |7 | uFIFO_RX |FIFO | 28| |8 | uBAUDGEN |BAUDGEN | 61| |9 | uUART_TX |UART_TX | 44| |10 | uFIFO_TX |FIFO_0 | 34| |11 | uUART_RX |UART_RX | 39| |12 | uAHB2LED |AHB2LED | 11| +------+----------------+-----------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:52 ; elapsed = 00:01:56 . Memory (MB): peak = 846.895 ; gain = 700.742 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 56 warnings. Synthesis Optimization Complete : Time (s): cpu = 00:01:52 ; elapsed = 00:01:56 . Memory (MB): peak = 846.895 ; gain = 700.742 INFO: [Netlist 29-17] Analyzing 23 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'AHBLITE_SYS' is not ideal for floorplanning, since the cellview 'cortexm0ds_logic' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: INFO: [Project 1-111] Unisim Transformation Summary: A total of 36 instances were transformed. INV => LUT1: 16 instances IOBUF => IOBUF (OBUFT, IBUF): 16 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances INFO: [Common 17-83] Releasing license: Synthesis 42 Infos, 162 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:06 ; elapsed = 00:02:10 . Memory (MB): peak = 1099.473 ; gain = 915.648 # write_checkpoint AHBLITE_SYS.dcp INFO: [Timing 38-35] Done setting XDC timing constraints. # report_utilization -file AHBLITE_SYS_utilization_synth.rpt -pb AHBLITE_SYS_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1099.473 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 13:32:03 2014...