*** Running vivado with args -log AHBLITE_SYS.rdi -applog -m64 -messageDb vivado.pb -mode batch -source AHBLITE_SYS.tcl -notrace ****** Vivado v2013.4 (64-bit) **** SW Build 353583 on Mon Dec 9 17:49:19 MST 2013 **** IP Build 208076 on Mon Dec 2 12:38:17 MST 2013 ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. Attempting to get a license: Implementation WARNING: [Common 17-301] Failed to get a license: Implementation WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation. Attempting to get a license: Synthesis WARNING: [Common 17-301] Failed to get a license: Synthesis Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] source AHBLITE_SYS.tcl -notrace INFO: [Project 1-11] Changing the constrs_type of fileset 'constrs_1' to 'XDC'. Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Netlist 29-17] Analyzing 23 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-43] Netlist 'AHBLITE_SYS' is not ideal for floorplanning, since the cellview 'cortexm0ds_logic' defined in file 'AHBLITE_SYS.edf' contains large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-479] Netlist was created with Vivado 2013.4 Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml... Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml Loading device configuration modes from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/Nexys4_Master.xdc] Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Source/Nexys4_Master.xdc] Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-5828-/dcp/AHBLITE_SYS.xdc] Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-5828-/dcp/AHBLITE_SYS.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: INFO: [Project 1-111] Unisim Transformation Summary: A total of 20 instances were transformed. IOBUF => IOBUF (OBUFT, IBUF): 16 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances link_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 861.102 ; gain = 677.652 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.132 . Memory (MB): peak = 863.160 ; gain = 2.059 Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: edb97bcd Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.436 . Memory (MB): peak = 869.730 ; gain = 6.570 Phase 2 Constant Propagation INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Opt 31-10] Eliminated 106 cells. Phase 2 Constant Propagation | Checksum: 19a0471bd Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.691 . Memory (MB): peak = 869.730 ; gain = 6.570 Phase 3 Sweep INFO: [Opt 31-12] Eliminated 233 unconnected nets. INFO: [Opt 31-11] Eliminated 2 unconnected cells. Phase 3 Sweep | Checksum: 20e64ccfd Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.890 . Memory (MB): peak = 869.730 ; gain = 6.570 Ending Logic Optimization Task | Checksum: 20e64ccfd Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.917 . Memory (MB): peak = 869.730 ; gain = 6.570 Implement Debug Cores | Checksum: 1afee0486 Logic Optimization | Checksum: 1afee0486 Starting Power Optimization Task Ending Power Optimization Task | Checksum: 20e64ccfd Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 869.730 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 21 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully INFO: [Timing 38-35] Done setting XDC timing constraints. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.147 . Memory (MB): peak = 873.156 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.1 Mandatory Logic Optimization INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.1 Mandatory Logic Optimization | Checksum: a22fbd0d Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.189 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.2 Build Super Logic Region (SLR) Database Phase 1.1.2 Build Super Logic Region (SLR) Database | Checksum: a22fbd0d Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.211 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.3 Add Constraints Phase 1.1.3 Add Constraints | Checksum: a22fbd0d Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.212 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.4 Build Macros Phase 1.1.4 Build Macros | Checksum: 17fde2ed8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.455 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.5 Implementation Feasibility check Phase 1.1.5 Implementation Feasibility check | Checksum: 17fde2ed8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.672 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.6 Pre-Place Cells Phase 1.1.6 Pre-Place Cells | Checksum: 17fde2ed8 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.684 . Memory (MB): peak = 875.152 ; gain = 0.000 Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 25de85b8b Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 877.082 ; gain = 1.930 Phase 1.1.8 Build Placer Netlist Model Phase 1.1.8.1 Place Init Design Phase 1.1.8.1.1 Build Clock Data Phase 1.1.8.1.1 Build Clock Data | Checksum: 2ceaccaef Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 885.039 ; gain = 9.887 Phase 1.1.8.1 Place Init Design | Checksum: 2884e7c89 Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 885.039 ; gain = 9.887 Phase 1.1.8 Build Placer Netlist Model | Checksum: 2884e7c89 Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 885.039 ; gain = 9.887 Phase 1.1.9 Constrain Clocks/Macros Phase 1.1.9.1 Constrain Global/Regional Clocks Phase 1.1.9.1 Constrain Global/Regional Clocks | Checksum: 2884e7c89 Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 885.039 ; gain = 9.887 Phase 1.1.9 Constrain Clocks/Macros | Checksum: 2884e7c89 Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 885.039 ; gain = 9.887 Phase 1.1 Placer Initialization Core | Checksum: 2884e7c89 Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 885.039 ; gain = 9.887 Phase 1 Placer Initialization | Checksum: 2884e7c89 Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 885.039 ; gain = 9.887 Phase 2 Global Placement Phase 2.1 Run Budgeter Phase 2.1 Run Budgeter | Checksum: 2d5013446 Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 890.445 ; gain = 15.293 Phase 2 Global Placement | Checksum: 2f45066e7 Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 890.445 ; gain = 15.293 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2f45066e7 Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 890.445 ; gain = 15.293 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1cf96de19 Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 890.445 ; gain = 15.293 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 2854c018e Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 890.445 ; gain = 15.293 Phase 3.4 Timing Path Optimizer Phase 3.4 Timing Path Optimizer | Checksum: 1d90fcbcd Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 890.445 ; gain = 15.293 Phase 3.5 Commit Small Macros & Core Logic Phase 3.5 Commit Small Macros & Core Logic | Checksum: 324f27556 Time (s): cpu = 00:00:17 ; elapsed = 00:00:13 . Memory (MB): peak = 896.383 ; gain = 21.230 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 324f27556 Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 896.383 ; gain = 21.230 Phase 3 Detail Placement | Checksum: 324f27556 Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 896.383 ; gain = 21.230 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 PCOPT Shape updates Phase 4.1 PCOPT Shape updates | Checksum: 2b7be596e Time (s): cpu = 00:00:18 ; elapsed = 00:00:13 . Memory (MB): peak = 896.383 ; gain = 21.230 Phase 4.2 Post Placement Optimization Phase 4.2.1 Post Placement Timing Optimization Phase 4.2.1 Post Placement Timing Optimization | Checksum: 248601e43 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.2 Post Placement Optimization | Checksum: 248601e43 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.3 Post Placement Cleanup Phase 4.3 Post Placement Cleanup | Checksum: 248601e43 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.4 Placer Reporting Phase 4.4.1 Congestion Reporting Phase 4.4.1 Congestion Reporting | Checksum: 248601e43 Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.4.2 updateTiming final Phase 4.4.2 updateTiming final | Checksum: 2a7236c9a Time (s): cpu = 00:00:20 ; elapsed = 00:00:14 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.4.3 Dump Critical Paths Phase 4.4.3 Dump Critical Paths | Checksum: 2a7236c9a Time (s): cpu = 00:00:20 ; elapsed = 00:00:14 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.4.4 Restore STA Phase 4.4.4 Restore STA | Checksum: 2a7236c9a Time (s): cpu = 00:00:20 ; elapsed = 00:00:15 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.4.5 Print Final WNS INFO: [Place 30-100] Post Placement Timing Summary | WNS=8.882 | TNS=0.000 | Phase 4.4.5 Print Final WNS | Checksum: 2a7236c9a Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.4 Placer Reporting | Checksum: 2a7236c9a Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4.5 Final Placement Cleanup Phase 4.5 Final Placement Cleanup | Checksum: 218a6738e Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 903.762 ; gain = 28.609 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 218a6738e Time (s): cpu = 00:00:21 ; elapsed = 00:00:15 . Memory (MB): peak = 903.762 ; gain = 28.609 Ending Placer Task | Checksum: 18ef2656e Time (s): cpu = 00:00:00 ; elapsed = 00:00:15 . Memory (MB): peak = 903.762 ; gain = 28.609 INFO: [Common 17-83] Releasing license: Implementation 32 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:16 . Memory (MB): peak = 903.762 ; gain = 30.605 INFO: [Timing 38-163] DEBUG : Generate clock report | CPU: 0 secs report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 903.762 ; gain = 0.000 INFO: [Designutils 20-134] DEBUG : Generate Control Sets report | CPU: 0 secs Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.540 . Memory (MB): peak = 903.762 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Starting Route Task Phase 1 Build RT Design Phase 1.1 Build Netlist & NodeGraph Phase 1.1 Build Netlist & NodeGraph | Checksum: 18ef2656e Time (s): cpu = 00:01:11 ; elapsed = 00:00:33 . Memory (MB): peak = 1068.371 ; gain = 142.543 Phase 1 Build RT Design | Checksum: fd0ca3ab Time (s): cpu = 00:01:11 ; elapsed = 00:00:33 . Memory (MB): peak = 1068.371 ; gain = 142.543 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: fd0ca3ab Time (s): cpu = 00:01:11 ; elapsed = 00:00:33 . Memory (MB): peak = 1068.371 ; gain = 142.543 Phase 2.2 Restore Routing Phase 2.2 Restore Routing | Checksum: fd0ca3ab Time (s): cpu = 00:01:11 ; elapsed = 00:00:33 . Memory (MB): peak = 1077.059 ; gain = 151.230 Phase 2.3 Special Net Routing Number of Nodes with overlaps = 0 Phase 2.3 Special Net Routing | Checksum: 158c1b524 Time (s): cpu = 00:01:11 ; elapsed = 00:00:33 . Memory (MB): peak = 1086.664 ; gain = 160.836 Phase 2.4 Local Clock Net Routing Phase 2.4 Local Clock Net Routing | Checksum: 158c1b524 Time (s): cpu = 00:01:11 ; elapsed = 00:00:33 . Memory (MB): peak = 1086.664 ; gain = 160.836 Phase 2.5 Update Timing Phase 2.5 Update Timing | Checksum: 158c1b524 Time (s): cpu = 00:01:13 ; elapsed = 00:00:34 . Memory (MB): peak = 1087.043 ; gain = 161.215 INFO: [Route 35-57] Estimated Timing Summary | WNS=8.8 | TNS=0 | WHS=0.007 | THS=0 | Phase 2.6 Budgeting Phase 2.6 Budgeting | Checksum: 158c1b524 Time (s): cpu = 00:01:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 2 Router Initialization | Checksum: 158c1b524 Time (s): cpu = 00:01:14 ; elapsed = 00:00:34 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: eca667d4 Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1.1 Remove Overlaps Number of Nodes with overlaps = 660 Number of Nodes with overlaps = 8 Number of Nodes with overlaps = 0 Phase 4.1.1 Remove Overlaps | Checksum: b1627e9d Time (s): cpu = 00:01:17 ; elapsed = 00:00:36 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 4.1.2 Update Timing Phase 4.1.2 Update Timing | Checksum: b1627e9d Time (s): cpu = 00:01:17 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 INFO: [Route 35-57] Estimated Timing Summary | WNS=8.31 | TNS=0 | WHS=N/A | THS=N/A | Phase 4.1.3 collectNewHoldAndFix Phase 4.1.3 collectNewHoldAndFix | Checksum: b1627e9d Time (s): cpu = 00:01:17 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 4.1 Global Iteration 0 | Checksum: b1627e9d Time (s): cpu = 00:01:17 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 4 Rip-up And Reroute | Checksum: b1627e9d Time (s): cpu = 00:01:17 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 5 Delay CleanUp Phase 5.1 Update Timing Phase 5.1 Update Timing | Checksum: b1627e9d Time (s): cpu = 00:01:18 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 INFO: [Route 35-57] Estimated Timing Summary | WNS=8.4 | TNS=0 | WHS=N/A | THS=N/A | Phase 5 Delay CleanUp | Checksum: b1627e9d Time (s): cpu = 00:01:18 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 6 Post Hold Fix Phase 6.1 Full Hold Analysis Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: b1627e9d Time (s): cpu = 00:01:18 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 INFO: [Route 35-57] Estimated Timing Summary | WNS=8.4 | TNS=0 | WHS=0.442 | THS=0 | Phase 6.1 Full Hold Analysis | Checksum: b1627e9d Time (s): cpu = 00:01:18 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 6 Post Hold Fix | Checksum: b1627e9d Time (s): cpu = 00:01:18 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 Router Utilization Summary Global Vertical Routing Utilization = 0.846412 % Global Horizontal Routing Utilization = 1.08859 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Verifying routed nets Verification completed successfully Phase 7 Verifying routed nets | Checksum: b1627e9d Time (s): cpu = 00:01:18 ; elapsed = 00:00:37 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 8 Depositing Routes Phase 8 Depositing Routes | Checksum: 6a476e3c Time (s): cpu = 00:01:19 ; elapsed = 00:00:38 . Memory (MB): peak = 1087.043 ; gain = 161.215 Phase 9 Post Router Timing INFO: [Route 35-20] Post Routing Timing Summary | WNS=8.429 | TNS=0.000 | WHS=0.460 | THS=0.000 | INFO: [Route 35-61] The design met the timing requirement. Phase 9 Post Router Timing | Checksum: 6a476e3c Time (s): cpu = 00:01:21 ; elapsed = 00:00:39 . Memory (MB): peak = 1087.043 ; gain = 161.215 INFO: [Route 35-16] Router Completed Successfully Ending Route Task | Checksum: 6a476e3c Time (s): cpu = 00:00:00 ; elapsed = 00:00:39 . Memory (MB): peak = 1087.043 ; gain = 161.215 Routing Is Done. Time (s): cpu = 00:00:00 ; elapsed = 00:00:39 . Memory (MB): peak = 1087.043 ; gain = 161.215 INFO: [Common 17-83] Releasing license: Implementation 47 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:23 ; elapsed = 00:00:40 . Memory (MB): peak = 1087.043 ; gain = 183.281 INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/impl_1/AHBLITE_SYS_drc_routed.rpt. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation report_power: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1087.043 ; gain = 0.000 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Constraints type: SDC. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.718 . Memory (MB): peak = 1087.043 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 13:33:42 2014... *** Running vivado with args -log AHBLITE_SYS.rdi -applog -m64 -messageDb vivado.pb -mode batch -source AHBLITE_SYS.tcl -notrace ****** Vivado v2013.4 (64-bit) **** SW Build 353583 on Mon Dec 9 17:49:19 MST 2013 **** IP Build 208076 on Mon Dec 2 12:38:17 MST 2013 ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. Attempting to get a license: Implementation WARNING: [Common 17-301] Failed to get a license: Implementation WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation. Attempting to get a license: Synthesis WARNING: [Common 17-301] Failed to get a license: Synthesis Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] source AHBLITE_SYS.tcl -notrace Command: open_checkpoint AHBLITE_SYS_routed.dcp INFO: [Netlist 29-17] Analyzing 24 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-43] Netlist 'AHBLITE_SYS' is not ideal for floorplanning, since the cellview 'cortexm0ds_logic' defined in file 'AHBLITE_SYS.edf' contains large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-479] Netlist was created with Vivado 2013.4 Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml... Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml Loading device configuration modes from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-2964-/dcp/AHBLITE_SYS.xdc] Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-2964-/dcp/AHBLITE_SYS.xdc] Reading XDEF placement. Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.206 . Memory (MB): peak = 861.547 ; gain = 0.578 Restoring placement. Restored 1034 out of 1034 XDEF sites from archive | CPU: 1.000000 secs | Memory: 0.000000 MB | INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: INFO: [Project 1-111] Unisim Transformation Summary: A total of 20 instances were transformed. IOBUF => IOBUF (OBUFT, IBUF): 16 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances INFO: [Project 1-484] Checkpoint was created with build 353583 open_checkpoint: Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 864.887 ; gain = 681.750 Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings, 1 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./AHBLITE_SYS.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P7/Lab/FPGA/Nexys4/Nexys4.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Apr 13 13:36:53 2014. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2013.4/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 1223.324 ; gain = 358.438 INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 13:36:53 2014...