*** Running vivado
    with args -log AHBLITE_SYS.rdi -applog -m64 -messageDb vivado.pb -mode batch -source AHBLITE_SYS.tcl -notrace


****** Vivado v2013.4 (64-bit)
  **** SW Build 353583 on Mon Dec  9 17:49:19 MST 2013
  **** IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: Implementation
WARNING: [Common 17-301] Failed to get a license: Implementation
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.

Attempting to get a license: Synthesis
WARNING: [Common 17-301] Failed to get a license: Synthesis
Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source AHBLITE_SYS.tcl -notrace
INFO: [Project 1-11] Changing the constrs_type of fileset 'constrs_1' to 'XDC'.
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 519 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2013.4
Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml
Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml
Loading device configuration modes from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Source/Nexys4_Master.xdc]
Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Source/Nexys4_Master.xdc]
Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-11800-/dcp/AHBLITE_SYS.xdc]
Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-11800-/dcp/AHBLITE_SYS.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 516 instances were transformed.
  RAM256X1S => RAM256X1S (RAMS64E, RAMS64E, RAMS64E, RAMS64E, MUXF7, MUXF7, MUXF8): 512 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances

link_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 870.813 ; gain = 687.492
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 872.641 ; gain = 1.828

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 1 Retarget

INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1dad71bce

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.925 . Memory (MB): peak = 884.527 ; gain = 11.887

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Opt 31-10] Eliminated 109 cells.
Phase 2 Constant Propagation | Checksum: 226662ec0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 884.527 ; gain = 11.887

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 236 unconnected nets.
INFO: [Opt 31-11] Eliminated 2 unconnected cells.
Phase 3 Sweep | Checksum: 1ec42676a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 884.527 ; gain = 11.887
Ending Logic Optimization Task | Checksum: 1ec42676a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 884.527 ; gain = 11.887
Implement Debug Cores | Checksum: 2733096a2
Logic Optimization | Checksum: 2733096a2

Starting Power Optimization Task
Ending Power Optimization Task | Checksum: 1ec42676a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 884.527 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
INFO: [Timing 38-35] Done setting XDC timing constraints.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.151 . Memory (MB): peak = 887.547 ; gain = 1.145
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 889.762 ; gain = 0.000

Phase 1.1.1 Mandatory Logic Optimization
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 889.762 ; gain = 0.000
Phase 1.1.1 Mandatory Logic Optimization | Checksum: b5e88eb4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.249 . Memory (MB): peak = 889.762 ; gain = 0.000

Phase 1.1.2 Build Super Logic Region (SLR) Database
Phase 1.1.2 Build Super Logic Region (SLR) Database | Checksum: b5e88eb4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.272 . Memory (MB): peak = 889.762 ; gain = 0.000

Phase 1.1.3 Add Constraints
Phase 1.1.3 Add Constraints | Checksum: b5e88eb4

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.273 . Memory (MB): peak = 889.762 ; gain = 0.000

Phase 1.1.4 Build Macros
Phase 1.1.4 Build Macros | Checksum: 13b3761ef

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.566 . Memory (MB): peak = 889.762 ; gain = 0.000

Phase 1.1.5 Implementation Feasibility check
Phase 1.1.5 Implementation Feasibility check | Checksum: 13b3761ef

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 889.762 ; gain = 0.000

Phase 1.1.6 Pre-Place Cells
Phase 1.1.6 Pre-Place Cells | Checksum: 13b3761ef

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 890.586 ; gain = 0.824

Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.1.7 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 165ff8ddf

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 891.512 ; gain = 1.750

Phase 1.1.8 Build Placer Netlist Model

Phase 1.1.8.1 Place Init Design

Phase 1.1.8.1.1 Build Clock Data
Phase 1.1.8.1.1 Build Clock Data | Checksum: 1d249d1bf

Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 906.109 ; gain = 16.348
Phase 1.1.8.1 Place Init Design | Checksum: 17cc29db9

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 906.109 ; gain = 16.348
Phase 1.1.8 Build Placer Netlist Model | Checksum: 17cc29db9

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 906.109 ; gain = 16.348

Phase 1.1.9 Constrain Clocks/Macros

Phase 1.1.9.1 Constrain Global/Regional Clocks
Phase 1.1.9.1 Constrain Global/Regional Clocks | Checksum: 17cc29db9

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 906.109 ; gain = 16.348
Phase 1.1.9 Constrain Clocks/Macros | Checksum: 17cc29db9

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 906.109 ; gain = 16.348
Phase 1.1 Placer Initialization Core | Checksum: 17cc29db9

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 906.109 ; gain = 16.348
Phase 1 Placer Initialization | Checksum: 17cc29db9

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 906.109 ; gain = 16.348

Phase 2 Global Placement

Phase 2.1 Run Budgeter
Phase 2.1 Run Budgeter | Checksum: 1a966b08a

Time (s): cpu = 00:00:14 ; elapsed = 00:00:11 . Memory (MB): peak = 914.055 ; gain = 24.293
Phase 2 Global Placement | Checksum: 197d41184

Time (s): cpu = 00:00:21 ; elapsed = 00:00:16 . Memory (MB): peak = 914.055 ; gain = 24.293

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 197d41184

Time (s): cpu = 00:00:22 ; elapsed = 00:00:16 . Memory (MB): peak = 914.055 ; gain = 24.293

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22fd70649

Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 914.055 ; gain = 24.293

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2a65da1b3

Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 914.055 ; gain = 24.293

Phase 3.4 Timing Path Optimizer
Phase 3.4 Timing Path Optimizer | Checksum: 277e7ea19

Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 914.055 ; gain = 24.293

Phase 3.5 Commit Small Macros & Core Logic
Phase 3.5 Commit Small Macros & Core Logic | Checksum: 1f9756042

Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 920.137 ; gain = 30.375

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1f9756042

Time (s): cpu = 00:00:26 ; elapsed = 00:00:20 . Memory (MB): peak = 921.215 ; gain = 31.453
Phase 3 Detail Placement | Checksum: 1f9756042

Time (s): cpu = 00:00:26 ; elapsed = 00:00:20 . Memory (MB): peak = 921.215 ; gain = 31.453

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 PCOPT Shape updates
Phase 4.1 PCOPT Shape updates | Checksum: 16cefc894

Time (s): cpu = 00:00:26 ; elapsed = 00:00:20 . Memory (MB): peak = 921.215 ; gain = 31.453

Phase 4.2 Post Placement Optimization

Phase 4.2.1 Post Placement Timing Optimization
Phase 4.2.1 Post Placement Timing Optimization | Checksum: 1793ca0b7

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 935.996 ; gain = 46.234
Phase 4.2 Post Placement Optimization | Checksum: 1793ca0b7

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 935.996 ; gain = 46.234

Phase 4.3 Post Placement Cleanup
Phase 4.3 Post Placement Cleanup | Checksum: 1793ca0b7

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 935.996 ; gain = 46.234

Phase 4.4 Placer Reporting

Phase 4.4.1 Congestion Reporting
Phase 4.4.1 Congestion Reporting | Checksum: 1793ca0b7

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 935.996 ; gain = 46.234

Phase 4.4.2 updateTiming final
Phase 4.4.2 updateTiming final | Checksum: 228209608

Time (s): cpu = 00:00:31 ; elapsed = 00:00:23 . Memory (MB): peak = 935.996 ; gain = 46.234

Phase 4.4.3 Dump Critical Paths 
Phase 4.4.3 Dump Critical Paths  | Checksum: 228209608

Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 935.996 ; gain = 46.234

Phase 4.4.4 Restore STA
Phase 4.4.4 Restore STA | Checksum: 228209608

Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 935.996 ; gain = 46.234

Phase 4.4.5 Print Final WNS
INFO: [Place 30-100] Post Placement Timing Summary | WNS=8.882  | TNS=0.000  |

Phase 4.4.5 Print Final WNS | Checksum: 228209608

Time (s): cpu = 00:00:35 ; elapsed = 00:00:26 . Memory (MB): peak = 936.816 ; gain = 47.055
Phase 4.4 Placer Reporting | Checksum: 228209608

Time (s): cpu = 00:00:35 ; elapsed = 00:00:26 . Memory (MB): peak = 936.816 ; gain = 47.055

Phase 4.5 Final Placement Cleanup
Phase 4.5 Final Placement Cleanup | Checksum: 229de44fb

Time (s): cpu = 00:00:36 ; elapsed = 00:00:26 . Memory (MB): peak = 936.816 ; gain = 47.055
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 229de44fb

Time (s): cpu = 00:00:36 ; elapsed = 00:00:26 . Memory (MB): peak = 936.816 ; gain = 47.055
Ending Placer Task | Checksum: 1479cbd74

Time (s): cpu = 00:00:00 ; elapsed = 00:00:26 . Memory (MB): peak = 936.816 ; gain = 47.055
INFO: [Common 17-83] Releasing license: Implementation
32 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:27 . Memory (MB): peak = 936.816 ; gain = 49.270
INFO: [Timing 38-163] DEBUG : Generate clock report | CPU: 0 secs 

report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.115 . Memory (MB): peak = 936.816 ; gain = 0.000
INFO: [Designutils 20-134] DEBUG : Generate Control Sets report | CPU: 0 secs 
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.739 . Memory (MB): peak = 936.816 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Starting Route Task

Phase 1 Build RT Design

Phase 1.1 Build Netlist & NodeGraph
Phase 1.1 Build Netlist & NodeGraph | Checksum: 1479cbd74

Time (s): cpu = 00:01:10 ; elapsed = 00:00:32 . Memory (MB): peak = 1091.816 ; gain = 142.086
Phase 1 Build RT Design | Checksum: 79308c51

Time (s): cpu = 00:01:10 ; elapsed = 00:00:32 . Memory (MB): peak = 1091.816 ; gain = 142.086

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 79308c51

Time (s): cpu = 00:01:10 ; elapsed = 00:00:32 . Memory (MB): peak = 1091.816 ; gain = 142.086

Phase 2.2 Restore Routing
Phase 2.2 Restore Routing | Checksum: 79308c51

Time (s): cpu = 00:01:10 ; elapsed = 00:00:32 . Memory (MB): peak = 1098.996 ; gain = 149.266

Phase 2.3 Special Net Routing
 Number of Nodes with overlaps = 0
Phase 2.3 Special Net Routing | Checksum: 1837f9d12

Time (s): cpu = 00:01:10 ; elapsed = 00:00:33 . Memory (MB): peak = 1119.578 ; gain = 169.848

Phase 2.4 Local Clock Net Routing
Phase 2.4 Local Clock Net Routing | Checksum: 1837f9d12

Time (s): cpu = 00:01:10 ; elapsed = 00:00:33 . Memory (MB): peak = 1119.578 ; gain = 169.848

Phase 2.5 Update Timing
Phase 2.5 Update Timing | Checksum: 1837f9d12

Time (s): cpu = 00:01:16 ; elapsed = 00:00:36 . Memory (MB): peak = 1120.781 ; gain = 171.051
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.8    | TNS=0      | WHS=0.007  | THS=0      |


Phase 2.6 Budgeting
Phase 2.6 Budgeting | Checksum: 1837f9d12

Time (s): cpu = 00:01:17 ; elapsed = 00:00:36 . Memory (MB): peak = 1121.023 ; gain = 171.293
Phase 2 Router Initialization | Checksum: 1837f9d12

Time (s): cpu = 00:01:17 ; elapsed = 00:00:36 . Memory (MB): peak = 1121.023 ; gain = 171.293

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 16f44fa9d

Time (s): cpu = 00:01:22 ; elapsed = 00:00:39 . Memory (MB): peak = 1145.785 ; gain = 196.055

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0

Phase 4.1.1 Remove Overlaps
 Number of Nodes with overlaps = 849
 Number of Nodes with overlaps = 10
 Number of Nodes with overlaps = 0
Phase 4.1.1 Remove Overlaps | Checksum: 13af0270e

Time (s): cpu = 00:01:26 ; elapsed = 00:00:42 . Memory (MB): peak = 1145.785 ; gain = 196.055

Phase 4.1.2 Update Timing
Phase 4.1.2 Update Timing | Checksum: 13af0270e

Time (s): cpu = 00:01:28 ; elapsed = 00:00:43 . Memory (MB): peak = 1145.785 ; gain = 196.055
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.04   | TNS=0      | WHS=N/A    | THS=N/A    |


Phase 4.1.3 collectNewHoldAndFix
Phase 4.1.3 collectNewHoldAndFix | Checksum: 13af0270e

Time (s): cpu = 00:01:28 ; elapsed = 00:00:43 . Memory (MB): peak = 1145.785 ; gain = 196.055
Phase 4.1 Global Iteration 0 | Checksum: 13af0270e

Time (s): cpu = 00:01:28 ; elapsed = 00:00:43 . Memory (MB): peak = 1145.785 ; gain = 196.055
Phase 4 Rip-up And Reroute | Checksum: 13af0270e

Time (s): cpu = 00:01:28 ; elapsed = 00:00:43 . Memory (MB): peak = 1145.785 ; gain = 196.055

Phase 5 Delay CleanUp

Phase 5.1 Update Timing
Phase 5.1 Update Timing | Checksum: 13af0270e

Time (s): cpu = 00:01:28 ; elapsed = 00:00:43 . Memory (MB): peak = 1145.785 ; gain = 196.055
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.13   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 5 Delay CleanUp | Checksum: 13af0270e

Time (s): cpu = 00:01:28 ; elapsed = 00:00:43 . Memory (MB): peak = 1145.785 ; gain = 196.055

Phase 6 Post Hold Fix

Phase 6.1 Full Hold Analysis

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 13af0270e

Time (s): cpu = 00:01:29 ; elapsed = 00:00:44 . Memory (MB): peak = 1145.785 ; gain = 196.055
INFO: [Route 35-57] Estimated Timing Summary | WNS=8.13   | TNS=0      | WHS=0.571  | THS=0      |

Phase 6.1 Full Hold Analysis | Checksum: 13af0270e

Time (s): cpu = 00:01:29 ; elapsed = 00:00:44 . Memory (MB): peak = 1145.785 ; gain = 196.055
Phase 6 Post Hold Fix | Checksum: 13af0270e

Time (s): cpu = 00:01:29 ; elapsed = 00:00:44 . Memory (MB): peak = 1145.785 ; gain = 196.055

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.36641 %
  Global Horizontal Routing Utilization  = 1.76904 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0


Phase 7 Verifying routed nets

 Verification completed successfully
Phase 7 Verifying routed nets | Checksum: 13af0270e

Time (s): cpu = 00:01:29 ; elapsed = 00:00:44 . Memory (MB): peak = 1145.785 ; gain = 196.055

Phase 8 Depositing Routes
Phase 8 Depositing Routes | Checksum: e403714f

Time (s): cpu = 00:01:30 ; elapsed = 00:00:44 . Memory (MB): peak = 1145.785 ; gain = 196.055

Phase 9 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=8.161  | TNS=0.000  | WHS=0.588  | THS=0.000  |

INFO: [Route 35-61] The design met the timing requirement.
Phase 9 Post Router Timing | Checksum: e403714f

Time (s): cpu = 00:01:37 ; elapsed = 00:00:50 . Memory (MB): peak = 1145.785 ; gain = 196.055
INFO: [Route 35-16] Router Completed Successfully
Ending Route Task | Checksum: e403714f

Time (s): cpu = 00:00:00 ; elapsed = 00:00:50 . Memory (MB): peak = 1145.785 ; gain = 196.055

Routing Is Done.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:50 . Memory (MB): peak = 1145.785 ; gain = 196.055
INFO: [Common 17-83] Releasing license: Implementation
47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 1145.785 ; gain = 208.969
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/AHBLITE_SYS_drc_routed.rpt.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
report_power: Time (s): cpu = 00:00:31 ; elapsed = 00:00:23 . Memory (MB): peak = 1145.785 ; gain = 0.000
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Constraints type: SDC.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1145.785 ; gain = 0.000
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./AHBLITE_SYS.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Apr 13 17:33:23 2014. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2013.4/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1309.648 ; gain = 163.863
INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 17:33:23 2014...

*** Running vivado
    with args -log AHBLITE_SYS.rdi -applog -m64 -messageDb vivado.pb -mode batch -source AHBLITE_SYS.tcl -notrace


****** Vivado v2013.4 (64-bit)
  **** SW Build 353583 on Mon Dec  9 17:49:19 MST 2013
  **** IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
    ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: Implementation
WARNING: [Common 17-301] Failed to get a license: Implementation
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.

Attempting to get a license: Synthesis
WARNING: [Common 17-301] Failed to get a license: Synthesis
Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
source AHBLITE_SYS.tcl -notrace
Command: open_checkpoint AHBLITE_SYS_routed.dcp
INFO: [Netlist 29-17] Analyzing 519 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2013.4
Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml
Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml
Loading device configuration modes from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml
Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/SoC Workshop Material/Solutions/P7-BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-3516-/dcp/AHBLITE_SYS.xdc]
Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/SoC Workshop Material/Solutions/P7-BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-3516-/dcp/AHBLITE_SYS.xdc]
Reading XDEF placement.
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.291 . Memory (MB): peak = 874.680 ; gain = 4.652
Restoring placement.
Restored 1503 out of 1503 XDEF sites from archive | CPU: 1.000000 secs | Memory: 0.000000 MB |
INFO: [Opt 31-138] Pushed 0 inverter(s).
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: 
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 516 instances were transformed.
  RAM256X1S => RAM256X1S (RAMS64E, RAMS64E, RAMS64E, RAMS64E, MUXF7, MUXF7, MUXF8): 512 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances

INFO: [Project 1-484] Checkpoint was created with build 353583
open_checkpoint: Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 879.758 ; gain = 696.184
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./AHBLITE_SYS.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] 'C:/Users/karshi01/Desktop/Workshop/SoC Workshop Material/Solutions/P7-BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Apr 13 23:06:05 2014. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2013.4/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 1242.336 ; gain = 362.578
INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 23:06:05 2014...