F
Command: %s
53*	vivadotcl2

opt_design2default:defaultZ4-113
›

@Attempting to get a license for feature '%s' and/or device '%s'
308*common2"
Implementation2default:default2
xc7a100t2default:defaultZ17-347
‹

0Got license for feature '%s' and/or device '%s'
310*common2"
Implementation2default:default2
xc7a100t2default:defaultZ17-349
e
,Running DRC as a precondition to command %s
22*	vivadotcl2

opt_design2default:defaultZ4-22
I

Starting %s Task
103*constraints2
DRC2default:defaultZ18-103
G
Running DRC with %s threads
24*drc2

22default:defaultZ23-27
L
DRC finished with %s
272*project2
0 Errors2default:defaultZ1-461
[
BPlease refer to the DRC report (report_drc) for more information.
274*projectZ1-462
‰


%s
*constraints2r
^Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 872.641 ; gain = 1.8282default:default
X

Starting %s Task
103*constraints2&
Logic Optimization2default:defaultZ18-103
<
%Done setting XDC timing constraints.
35*timingZ38-35
`

Phase %s%s
101*constraints2
1 2default:default2
Retarget2default:defaultZ18-101
C
Pushed %s inverter(s).
98*opt2

02default:defaultZ31-138
B
Retargeted %s cell(s).
49*opt2

02default:defaultZ31-49
3
'Phase 1 Retarget | Checksum: 1dad71bce
*common
Š


%s
*constraints2s
_Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.925 . Memory (MB): peak = 884.527 ; gain = 11.8872default:default
l

Phase %s%s
101*constraints2
2 2default:default2(
Constant Propagation2default:defaultZ18-101
C
Pushed %s inverter(s).
98*opt2

02default:defaultZ31-138
B
Eliminated %s cells.
10*opt2
1092default:defaultZ31-10
?
3Phase 2 Constant Propagation | Checksum: 226662ec0
*common
†


%s
*constraints2o
[Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 884.527 ; gain = 11.8872default:default
]

Phase %s%s
101*constraints2
3 2default:default2
Sweep2default:defaultZ18-101
M
 Eliminated %s unconnected nets.
12*opt2
2362default:defaultZ31-12
L
!Eliminated %s unconnected cells.
11*opt2

22default:defaultZ31-11
0
$Phase 3 Sweep | Checksum: 1ec42676a
*common
†


%s
*constraints2o
[Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 884.527 ; gain = 11.8872default:default
A
5Ending Logic Optimization Task | Checksum: 1ec42676a
*common
†


%s
*constraints2o
[Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 884.527 ; gain = 11.8872default:default
8
,Implement Debug Cores | Checksum: 2733096a2
*common
5
)Logic Optimization | Checksum: 2733096a2
*common
X

Starting %s Task
103*constraints2&
Power Optimization2default:defaultZ18-103
A
5Ending Power Optimization Task | Checksum: 1ec42676a
*common
‰


%s
*constraints2r
^Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 884.527 ; gain = 0.0002default:default
Q
Releasing license: %s
83*common2"
Implementation2default:defaultZ17-83
½

G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
212default:default2

02default:default2

02default:default2

02default:defaultZ4-41
S
%s completed successfully
29*	vivadotcl2

opt_design2default:defaultZ4-42
<
%Done setting XDC timing constraints.
35*timingZ38-35
4
Writing XDEF routing.
211*designutilsZ20-211
A
#Writing XDEF routing logical nets.
209*designutilsZ20-209
A
#Writing XDEF routing special nets.
210*designutilsZ20-210
…
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2)
Write XDEF Complete: 2default:default2
00:00:012default:default2 
00:00:00.1512default:default2
887.5472default:default2
1.1452default:defaultZ17-268


End Record