‚ 3Changing the constrs_type of fileset '%s' to '%s'. 11*project2 constrs_12default:default2 XDC2default:defaultZ1-11 ^ #Design is defaulting to srcset: %s 437* planAhead2 sources_12default:defaultZ12-437 a &Design is defaulting to constrset: %s 434* planAhead2 constrs_12default:defaultZ12-434 ^ -Analyzing %s Unisim elements for replacement 17*netlist2 5192default:defaultZ29-17 a 2Unisim Transformation completed in %s CPU seconds 28*netlist2 02default:defaultZ29-28 o Netlist was created with %s %s291*project2 Vivado2default:default2 2013.42default:defaultZ1-479 › Loading clock regions from %s 13*device2d PC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml2default:defaultZ21-13 œ Loading clock buffers from %s 11*device2e QC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml2default:defaultZ21-11 ™ &Loading clock placement rules from %s 318*place2Y EC:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml2default:defaultZ30-318 — )Loading package pin functions from %s... 17*device2U AC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml2default:defaultZ21-17 ˜ Loading package from %s 16*device2g SC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml2default:defaultZ21-16 Œ Loading io standards from %s 15*device2V BC:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml2default:defaultZ21-15 ˜ +Loading device configuration modes from %s 14*device2T @C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml2default:defaultZ21-14 ^ 1Inserted %s IBUFs to IO ports without IO buffers.100*opt2 02default:defaultZ31-140 ^ 1Inserted %s OBUFs to IO ports without IO buffers.101*opt2 02default:defaultZ31-141 ¿ Parsing XDC File [%s] 179* designutils2ˆ tC:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Source/Nexys4_Master.xdc2default:defaultZ20-179 È Finished Parsing XDC File [%s] 178* designutils2ˆ tC:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Source/Nexys4_Master.xdc2default:defaultZ20-178 è Parsing XDC File [%s] 179* designutils2± œC:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-11800-/dcp/AHBLITE_SYS.xdc2default:defaultZ20-179 ñ Finished Parsing XDC File [%s] 178* designutils2± œC:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final3 - Gold/P7/Lab - BRAM/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-11800-/dcp/AHBLITE_SYS.xdc2default:defaultZ20-178 C Pushed %s inverter(s). 98*opt2 02default:defaultZ31-138 | MSuccessfully populated the BRAM INIT strings from the following elf files: %s96*memdata2 2default:defaultZ28-144  !Unisim Transformation Summary: %s111*project2… ð A total of 516 instances were transformed. RAM256X1S => RAM256X1S (RAMS64E, RAMS64E, RAMS64E, RAMS64E, MUXF7, MUXF7, MUXF8): 512 instances RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 4 instances 2default:defaultZ1-111 û I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2! link_design: 2default:default2 00:00:192default:default2 00:00:192default:default2 870.8132default:default2 687.4922default:defaultZ17-268  End Record