*** Running vivado with args -log AHBLITE_SYS.rds -m64 -mode batch -messageDb vivado.pb -source AHBLITE_SYS.tcl ****** Vivado v2013.4 (64-bit) **** SW Build 353583 on Mon Dec 9 17:49:19 MST 2013 **** IP Build 208076 on Mon Dec 2 12:38:17 MST 2013 ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. Attempting to get a license: Implementation WARNING: [Common 17-301] Failed to get a license: Implementation WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation. Attempting to get a license: Synthesis WARNING: [Common 17-301] Failed to get a license: Synthesis Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml] source AHBLITE_SYS.tcl # set_param gui.test TreeTableDev # set_msg_config -id {HDL 9-1061} -limit 100000 # set_msg_config -id {HDL 9-1654} -limit 100000 # create_project -in_memory -part xc7a100tcsg324-1 # set_property target_language Verilog [current_project] # set_param project.compositeFile.enableAutoGeneration 0 # read_verilog { # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/cortexm0ds_logic.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/CORTEXM0DS.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBMUX.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBDCD.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2LED.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2BRAM.v} # {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v} # } # read_xdc {{C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/Nexys4_Master.xdc}} INFO: [Project 1-11] Changing the constrs_type of fileset 'constrs_1' to 'XDC'. # set_property used_in_implementation false [get_files {{C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/Nexys4_Master.xdc}}] # set_param synth.vivado.isSynthRun true # set_property webtalk.parent_dir {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Nexys4/Nexys4.data/wt} [current_project] # set_property parent.project_dir {C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Nexys4} [current_project] # synth_design -top AHBLITE_SYS -part xc7a100tcsg324-1 Command: synth_design -top AHBLITE_SYS -part xc7a100tcsg324-1 Starting synthesis... Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 237.285 ; gain = 90.762 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'AHBLITE_SYS' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:38] INFO: [Synth 8-638] synthesizing module 'BUFG' [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:612] INFO: [Synth 8-256] done synthesizing module 'BUFG' (1#1) [C:/Xilinx/Vivado/2013.4/scripts/rt/data/unisim_comp.v:612] INFO: [Synth 8-638] synthesizing module 'CORTEXM0DS' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/CORTEXM0DS.v:27] INFO: [Synth 8-638] synthesizing module 'cortexm0ds_logic' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/cortexm0ds_logic.v:27] INFO: [Synth 8-256] done synthesizing module 'cortexm0ds_logic' (2#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/cortexm0ds_logic.v:27] INFO: [Synth 8-256] done synthesizing module 'CORTEXM0DS' (3#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/CORTEXM0DS.v:27] INFO: [Synth 8-638] synthesizing module 'AHBDCD' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBDCD.v:38] INFO: [Synth 8-256] done synthesizing module 'AHBDCD' (4#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBDCD.v:38] INFO: [Synth 8-638] synthesizing module 'AHBMUX' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBMUX.v:38] INFO: [Synth 8-256] done synthesizing module 'AHBMUX' (5#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBMUX.v:38] INFO: [Synth 8-638] synthesizing module 'AHB2MEM' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2BRAM.v:11] Parameter MEMWIDTH bound to: 10 - type: integer INFO: [Synth 8-3876] $readmem data file '../../Software/code.hex' is read successfully [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2BRAM.v:53] INFO: [Synth 8-256] done synthesizing module 'AHB2MEM' (6#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2BRAM.v:11] WARNING: [Synth 8-350] instance 'uAHB2MEM' of module 'AHB2MEM' requires 12 connections, but only 11 given [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:201] INFO: [Synth 8-638] synthesizing module 'AHB2LED' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2LED.v:1] INFO: [Synth 8-256] done synthesizing module 'AHB2LED' (7#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2LED.v:1] INFO: [Synth 8-256] done synthesizing module 'AHBLITE_SYS' (8#1) [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:38] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 438.188 ; gain = 291.664 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[27] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[26] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[25] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[24] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[23] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[22] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[21] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[20] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[19] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[18] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[17] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[16] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[15] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[14] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[13] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[12] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[11] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[10] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[9] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[8] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[7] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[6] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[5] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[4] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[3] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[2] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[1] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S2[0] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[27] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[26] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[25] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[24] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[23] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[22] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[21] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[20] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[19] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[18] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[17] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[16] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[15] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[14] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[13] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[12] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[11] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[10] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[9] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[8] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[7] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[6] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[5] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[4] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[3] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[2] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[1] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S3[0] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[27] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[26] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[25] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[24] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[23] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[22] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[21] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[20] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[19] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[18] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[17] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[16] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[15] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[14] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[13] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[12] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[11] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[10] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[9] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[8] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[7] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[6] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[5] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[4] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[3] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[2] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[1] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S4[0] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[31] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[30] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[29] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] WARNING: [Synth 8-3295] tying undriven pin uAHBMUX:HRDATA_S5[28] to constant 0 [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHBLITE_SYS.v:164] INFO: [Common 17-14] Message 'Synth 8-3295' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading clock regions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml Loading clock buffers from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml Loading clock placement rules from C:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml Loading package pin functions from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml... Loading package from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml Loading io standards from C:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml Loading device configuration modes from C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml Processing XDC Constraints Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/Nexys4_Master.xdc] Finished Parsing XDC File [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/Nexys4_Master.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Nexys4/Nexys4.runs/synth_1/.Xil/AHBLITE_SYS_propImpl.xdc]. Resolution: To avoid this message, exclude constraints listed in [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Nexys4/Nexys4.runs/synth_1/.Xil/AHBLITE_SYS_propImpl.xdc] from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Start RTL Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 616.363 ; gain = 469.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 616.363 ; gain = 469.840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:55 ; elapsed = 00:00:57 . Memory (MB): peak = 616.363 ; gain = 469.840 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 34 Bit Adders := 2 2 Input 31 Bit Adders := 1 2 Input 30 Bit Adders := 1 2 Input 24 Bit Adders := 1 2 Input 9 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 59 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 1 2 Bit Registers := 2 1 Bit Registers := 844 +---RAMs : 8K Bit RAMs := 1 +---Muxes : 11 Input 16 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 11 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 386 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module AHBLITE_SYS Detailed RTL Component Info : +---Registers : 1 Bit Registers := 1 Module cortexm0ds_logic Detailed RTL Component Info : +---Adders : 2 Input 34 Bit Adders := 2 2 Input 31 Bit Adders := 1 2 Input 30 Bit Adders := 1 2 Input 24 Bit Adders := 1 2 Input 9 Bit Adders := 1 +---XORs : 2 Input 1 Bit XORs := 59 +---Registers : 1 Bit Registers := 839 +---Muxes : 2 Input 1 Bit Muxes := 386 Module CORTEXM0DS Detailed RTL Component Info : Module AHBDCD Detailed RTL Component Info : +---Muxes : 11 Input 16 Bit Muxes := 1 11 Input 4 Bit Muxes := 1 Module AHBMUX Detailed RTL Component Info : +---Registers : 4 Bit Registers := 1 +---Muxes : 11 Input 1 Bit Muxes := 1 Module AHB2MEM Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 3 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 +---RAMs : 8K Bit RAMs := 1 Module AHB2LED Detailed RTL Component Info : +---Registers : 8 Bit Registers := 1 2 Bit Registers := 1 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[31] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[30] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[29] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[28] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[27] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[26] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[25] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[24] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[23] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[22] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[21] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[20] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[19] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[18] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[17] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[16] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[15] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[14] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[13] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[12] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[11] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[10] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HSIZE_reg[2] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HTRANS_reg[0] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2LED/rHTRANS_reg[0] ) is unused and will be removed from module AHBLITE_SYS. INFO: [Synth 8-4471] merging register 'uAHB2LED/rHWRITE_reg' into 'uAHB2MEM/APhase_HWRITE_reg' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2LED.v:40] INFO: [Synth 8-4471] merging register 'uAHB2LED/rHTRANS_reg[1:0]' into 'uAHB2MEM/APhase_HTRANS_reg[1:0]' [C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part2/FPGA/Source/AHB2LED.v:39] WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[31] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[30] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[29] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[28] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[27] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[26] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[25] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[24] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[23] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[22] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[21] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[20] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[19] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[18] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[17] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[16] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[15] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[14] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[13] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[12] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[11] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HADDR_reg[10] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HSIZE_reg[2] ) is unused and will be removed from module AHBLITE_SYS. WARNING: [Synth 8-3332] Sequential element (\uAHB2MEM/APhase_HTRANS_reg[0] ) is unused and will be removed from module AHBLITE_SYS. --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:56 ; elapsed = 00:00:58 . Memory (MB): peak = 626.027 ; gain = 479.504 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Distributed RAM: +------------+---------------------+--------------------+----------------------+------------------+--------------------+ |Module Name | RTL Object | Inference Criteria | Size (depth X width) | Primitives | Hierarchical Name | +------------+---------------------+--------------------+----------------------+------------------+--------------------+ |AHBLITE_SYS | uAHB2MEM/memory_reg | Implied | 256 X 32 | RAM256X1S x 32 | AHBLITE_SYS/ram__1 | +------------+---------------------+--------------------+----------------------+------------------+--------------------+ Note: Mutiple instantiated RAMs are reported only once. "Hierarchical Name" reflects the hierarchical modules names of the RAM and only part of it is displayed. --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-3333] propagating constant 0 across sequential element (\u_cortexm0ds/u_logic /Qnn2z4_reg) WARNING: [Synth 8-3332] Sequential element (Ypi3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Aii3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Q0f3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Mvi2z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (I6h3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Q4h3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (W8r2z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Jje3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Etq2z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (C7f3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Gzb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (O2c3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Rnb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (W5c3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Qsb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (E9c3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Zqb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Yvb3z4_reg) is unused and will be removed from module cortexm0ds_logic. WARNING: [Synth 8-3332] Sequential element (Qnn2z4_reg) is unused and will be removed from module cortexm0ds_logic. --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:01:30 ; elapsed = 00:01:32 . Memory (MB): peak = 766.586 ; gain = 620.063 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:30 ; elapsed = 00:01:32 . Memory (MB): peak = 766.586 ; gain = 620.063 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:31 ; elapsed = 00:01:33 . Memory (MB): peak = 766.586 ; gain = 620.063 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (\u_cortexm0ds/u_logic/Y9t2z4_reg ) is unused and will be removed from module AHBLITE_SYS. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:42 ; elapsed = 00:01:45 . Memory (MB): peak = 823.684 ; gain = 677.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Gated Clock Conversion mode: off --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:43 ; elapsed = 00:01:46 . Memory (MB): peak = 823.684 ; gain = 677.160 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:43 ; elapsed = 00:01:46 . Memory (MB): peak = 823.684 ; gain = 677.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:43 ; elapsed = 00:01:46 . Memory (MB): peak = 823.684 ; gain = 677.160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 2| |2 |CARRY4 | 40| |3 |LUT1 | 118| |4 |LUT2 | 308| |5 |LUT3 | 271| |6 |LUT4 | 321| |7 |LUT5 | 565| |8 |LUT6 | 1859| |9 |MUXF7 | 9| |10 |RAM256X1S | 32| |11 |FDCE | 145| |12 |FDPE | 704| |13 |FDRE | 1| |14 |IBUF | 2| |15 |OBUF | 9| +------+----------+------+ Report Instance Areas: +------+---------------+-----------------+------+ | |Instance |Module |Cells | +------+---------------+-----------------+------+ |1 |top | | 4386| |2 | uAHB2MEM |AHB2MEM | 59| |3 | uAHBMUX |AHBMUX | 53| |4 | u_cortexm0ds |CORTEXM0DS | 4248| |5 | u_logic |cortexm0ds_logic | 4237| |6 | uAHB2LED |AHB2LED | 9| +------+---------------+-----------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:44 ; elapsed = 00:01:47 . Memory (MB): peak = 823.684 ; gain = 677.160 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 69 warnings. Synthesis Optimization Complete : Time (s): cpu = 00:01:44 ; elapsed = 00:01:47 . Memory (MB): peak = 823.684 ; gain = 677.160 INFO: [Netlist 29-17] Analyzing 34 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'AHBLITE_SYS' is not ideal for floorplanning, since the cellview 'cortexm0ds_logic' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s). INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: INFO: [Project 1-111] Unisim Transformation Summary: A total of 32 instances were transformed. RAM256X1S => RAM256X1S (RAMS64E, RAMS64E, RAMS64E, RAMS64E, MUXF7, MUXF7, MUXF8): 32 instances INFO: [Common 17-83] Releasing license: Synthesis 32 Infos, 171 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:57 ; elapsed = 00:02:00 . Memory (MB): peak = 1083.777 ; gain = 900.582 # write_checkpoint AHBLITE_SYS.dcp INFO: [Timing 38-35] Done setting XDC timing constraints. # report_utilization -file AHBLITE_SYS_utilization_synth.rpt -pb AHBLITE_SYS_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1083.777 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 14:35:32 2014...