#-----------------------------------------------------------
# Vivado v2013.4 (64-bit)
# SW Build 353583 on Mon Dec  9 17:49:19 MST 2013
# IP Build 208076 on Mon Dec  2 12:38:17 MST 2013
# Start of session at: Sun Apr 13 16:26:53 2014
# Process ID: 11124
# Log file: C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Lab1/vivado.log
# Journal file: C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Lab1\vivado.jou
#-----------------------------------------------------------
Attempting to get a license: Implementation
WARNING: [Common 17-301] Failed to get a license: Implementation
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.

Attempting to get a license: Synthesis
WARNING: [Common 17-301] Failed to get a license: Synthesis
Loading parts and site information from C:/Xilinx/Vivado/2013.4/data/parts/arch.xml
Parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/Vivado/2013.4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
open_project {C:\Users\karshi01\Desktop\Workshop\USB\Full Material - V6 -Final2\Solutions\P6\Lab Part1\FPGA\Lab1\Lab1.xpr}
INFO: [Project 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Lab1'
INFO: [Project 1-313] Project file moved from 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part1/FPGA/Lab1' since last save.
CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Lab1/Lab1.srcs/sources_1/imports/Source/cortexm0ds_logic.v', nor could it be found using path 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part1/FPGA/Lab1/Lab1.srcs/sources_1/imports/Source/cortexm0ds_logic.v'.
Import path for source C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Lab1/Lab1.srcs/sources_1/imports/Source/cortexm0ds_logic.v: Could not find the file 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Source/cortexm0ds_logic.v', nor could it be found using path 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part1/FPGA/Source/cortexm0ds_logic.v'.
CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Lab1/Lab1.srcs/sources_1/imports/Source/CORTEXM0DS.v', nor could it be found using path 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part1/FPGA/Lab1/Lab1.srcs/sources_1/imports/Source/CORTEXM0DS.v'.
Import path for source C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Lab1/Lab1.srcs/sources_1/imports/Source/CORTEXM0DS.v: Could not find the file 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V6 -Final2/Solutions/P6/Lab Part1/FPGA/Source/CORTEXM0DS.v', nor could it be found using path 'C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/Solutions/P6/Lab Part1/FPGA/Source/CORTEXM0DS.v'.
Scanning sources...
Finished scanning sources
open_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 878.520 ; gain = 74.148
update_compile_order -fileset sources_1
exit
INFO: [Common 17-206] Exiting Vivado at Sun Apr 13 17:14:13 2014...