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module AHBLITE_SYS(
	//CLOCKS & RESET
	input		wire				CLK,
	input		wire				RESET, 
	
	//TO BOARD LEDs
	output 	wire	[7:0] 	LED,
	
	//TOWARDS MEMORY
	inout  	wire	[15:0] 	MemDB,
	output 	wire	[26:1] 	MemAdr,
	output 	wire				RamCS,
	output 	wire				FlashCS,
	output 	wire				MemWR,
	output 	wire				MemOE,
	output 	wire				RamUB,
	output 	wire				RamLB,
	output 	wire				RamCre,
	output 	wire				RamAdv,
	output 	wire				RamClk,
	input 	wire				RamWait,
	output 	wire				FlashRp,
	
	//VGA IO
	output	wire 	[2:0]		vga_red,
	output 	wire	[2:0]		vga_green,
	output 	wire	[1:0]		vga_blue,
   output 	wire				hsync,     	//VGA Horizontal Sync
   output 	wire				vsync,     	//VGA Vertical Sync
	
	//TO UART
	input 	wire				RsRx,
	output 	wire				RsTx,
	
	//Nexys Board Inputs
   input 	wire	[7:0]		sw,
	
	// 7 Segment display
	output 	wire	[6:0]		seg,
	output 	wire				dp,
	output 	wire	[3:0]		an
	
);
 
//AHB-LITE SIGNALS 
//Gloal Signals
wire 				HCLK;
wire 				HRESETn;
//Address, Control & Write Data Signals
wire [31:0]		HADDR;
wire [31:0]		HWDATA;
wire 				HWRITE;
wire [1:0] 		HTRANS;
wire [2:0] 		HBURST;
wire 				HMASTLOCK;
wire [3:0] 		HPROT;
wire [2:0] 		HSIZE;
//Transfer Response & Read Data Signals
wire [31:0] 	HRDATA;
wire 				HRESP;
wire 				HREADY;

//SELECT SIGNALS
wire [3:0] 		MUX_SEL;

wire 				HSEL_MEM;
wire 				HSEL_VGA;
wire 				HSEL_UART;
wire 				HSEL_GPIO;
wire 				HSEL_TIMER;
wire 				HSEL_7SEG;

//SLAVE READ DATA
wire [31:0] 	HRDATA_MEM;
wire [31:0] 	HRDATA_VGA;
wire [31:0] 	HRDATA_UART;
wire [31:0] 	HRDATA_GPIO;
wire [31:0] 	HRDATA_TIMER;
wire [31:0] 	HRDATA_7SEG;

//SLAVE HREADYOUT
wire 				HREADYOUT_MEM;
wire 				HREADYOUT_VGA;
wire 				HREADYOUT_UART;
wire 				HREADYOUT_GPIO;
wire 				HREADYOUT_TIMER;
wire 				HREADYOUT_7SEG;
//CM0-DS Sideband signals
wire 				LOCKUP;
wire 				TXEV;
wire 				SLEEPING;
wire [15:0]		IRQ;
  
//SYSTEM GENERATES NO ERROR RESPONSE
assign 			HRESP = 1'b0;

//CM0-DS INTERRUPT SIGNALS  
assign 			IRQ = {10'b0000_0000_00,4'b0000,1'b0,UART_IRQ,TIMER_IRQ};
//assign 			LED[7] = LOCKUP;

assign 			HRESETn = ~ RESET;

// Clock divider, divide the frequency by two, hence less time constraint 
reg clk_div;

  always @(posedge CLK)
  begin
    clk_div=~clk_div;
  end

// A global clock buffer
  BUFG BUFG_CLK (
      .O(HCLK), 		// 1-bit output: Clock buffer output
      .I(clk_div)  	// 1-bit input: Clock buffer input
  );


                 

//AHBLite MASTER --> CM0-DS

CORTEXM0DS u_cortexm0ds (
	//Global Signals
	.HCLK        (HCLK),
	.HRESETn     (HRESETn),
	//Address, Control & Write Data	
	.HADDR       (HADDR[31:0]),
	.HBURST      (HBURST[2:0]),
	.HMASTLOCK   (HMASTLOCK),
	.HPROT       (HPROT[3:0]),
	.HSIZE       (HSIZE[2:0]),
	.HTRANS      (HTRANS[1:0]),
	.HWDATA      (HWDATA[31:0]),
	.HWRITE      (HWRITE),
	//Transfer Response & Read Data	
	.HRDATA      (HRDATA[31:0]),			
	.HREADY      (HREADY),					
	.HRESP       (HRESP),					

	//CM0 Sideband Signals
	.NMI         (1'b0),
	.IRQ         (IRQ[15:0]),
	.TXEV        (),
	.RXEV        (1'b0),
	.LOCKUP      (LOCKUP),
	.SYSRESETREQ (),
	.SLEEPING    ()
);

//Address Decoder 

AHBDCD uAHBDCD (
	.HADDR(HADDR[31:0]),
	 
	.HSEL_S0(HSEL_MEM),
	.HSEL_S1(HSEL_VGA),
	.HSEL_S2(HSEL_UART),
	.HSEL_S3(HSEL_TIMER),
	.HSEL_S4(HSEL_GPIO),
	.HSEL_S5(HSEL_7SEG),
	.HSEL_S6(),
	.HSEL_S7(),
	.HSEL_S8(),
	.HSEL_S9(),
	.HSEL_NOMAP(HSEL_NOMAP),
	 
	.MUX_SEL(MUX_SEL[3:0])
);

//Slave to Master Mulitplexor

AHBMUX uAHBMUX (
	.HCLK(HCLK),
	.HRESETn(HRESETn),
	.MUX_SEL(MUX_SEL[3:0]),
	 
	.HRDATA_S0(HRDATA_MEM),
	.HRDATA_S1(HRDATA_VGA),
	.HRDATA_S2(HRDATA_UART),
	.HRDATA_S3(HRDATA_TIMER),
	.HRDATA_S4(HRDATA_GPIO),
	.HRDATA_S5(HRDATA_7SEG),
	.HRDATA_S6(),
	.HRDATA_S7(),
	.HRDATA_S8(),
	.HRDATA_S9(),
	.HRDATA_NOMAP(32'hDEADBEEF),
	 
	.HREADYOUT_S0(HREADYOUT_MEM),
	.HREADYOUT_S1(HREADYOUT_VGA),
	.HREADYOUT_S2(HREADYOUT_UART),
	.HREADYOUT_S3(HREADYOUT_TIMER),
	.HREADYOUT_S4(HREADYOUT_GPIO),
	.HREADYOUT_S5(HREADYOUT_7SEG),
	.HREADYOUT_S6(1'b1),
	.HREADYOUT_S7(1'b1),
	.HREADYOUT_S8(1'b1),
	.HREADYOUT_S9(1'b1),
	.HREADYOUT_NOMAP(1'b1),
    
	.HRDATA(HRDATA[31:0]),
	.HREADY(HREADY)
);

// AHBLite Peripherals


// AHBLite Memory Controller  
AHB2SRAMFLSH uAHB2SRAMFLSH (
	.HCLK(HCLK),
	.HRESETn(HRESETn), 
	.HADDR(HADDR[31:0]), 
	.HSEL(HSEL_MEM),
	.HREADY(HREADY),
	.HSIZE(HSIZE[2:0]), 
	.HTRANS(HTRANS[1:0]), 
	.HWDATA(HWDATA[31:0]), 
	.HWRITE(HWRITE), 
	.HRDATA(HRDATA_MEM[31:0]), 
	.HREADYOUT(HREADYOUT_MEM), 
 
	.FlashAtZero(0),
	
	.MemDB(MemDB), 
	.MemAdr(MemAdr[26:1]), 
	.RamCS(RamCS), 
	.FlashCS(FlashCS), 
	.MemWR(MemWR), 
	.MemOE(MemOE), 
	.RamUB(RamUB), 
	.RamLB(RamLB), 
	.RamCre(RamCre), 
	.RamAdv(RamAdv), 
	.RamClk(RamClk), 
	.RamWait(RamWait), 
	.FlashRp(FlashRp) 
);

// AHBLite VGA Pheripheral
AHBVGA uAHBVGA (
    .HCLK(HCLK), 
    .HRESETn(HRESETn), 
    .HADDR(HADDR), 
    .HWDATA(HWDATA), 
    .HREADY(HREADY), 
    .HWRITE(HWRITE), 
    .HTRANS(HTRANS), 
    .HSEL(HSEL_VGA), 
    .HRDATA(HRDATA_VGA), 
    .HREADYOUT(HREADYOUT_VGA), 
    .hsync(hsync), 
    .vsync(vsync), 
    .rgb({vga_red,vga_green,vga_blue})
    );


// AHBLite UART Pheripheral
AHBUART uAHBUART(
	.HCLK(HCLK),
	.HRESETn(HRESETn),
	.HADDR(HADDR[31:0]),
	.HTRANS(HTRANS[1:0]),
	.HWDATA(HWDATA[31:0]),
	.HWRITE(HWRITE),
	.HREADY(HREADY),
	.HREADYOUT(HREADYOUT_UART),
	.HRDATA(HRDATA_UART[31:0]),
	.HSEL(HSEL_UART),
	
	.RsRx(RsRx),
	.RsTx(RsTx),
	.uart_irq(UART_IRQ)
    );

// AHBLite 7-segment Pheripheral	 
	 AHB7SEGDEC uAHB7SEGDEC(
	 .HCLK(HCLK),
	 .HRESETn(HRESETn),
	 .HADDR(HADDR[31:0]),
	 .HTRANS(HTRANS[1:0]),
	 .HWDATA(HWDATA[31:0]),
	 .HWRITE(HWRITE),
	 .HREADY(HREADY),
	 .HREADYOUT(HREADYOUT_7SEG),
	 .HRDATA(HRDATA_7SEG[31:0]),
	 .HSEL(HSEL_7SEG),
	 
	 .seg(seg),
	 .an(an),
	 .dp(dp)
		);	
		
// AHBLite timer
    AHBTIMER uAHBTIMER(
    .HCLK(HCLK),
    .HRESETn(HRESETn),
    .HADDR(HADDR[31:0]),
    .HTRANS(HTRANS[1:0]),
    .HWDATA(HWDATA[31:0]),
    .HWRITE(HWRITE),
    .HREADY(HREADY),
    .HREADYOUT(HREADYOUT_TIMER),
    .HRDATA(HRDATA_TIMER[31:0]),
    .HSEL(HSEL_TIMER),
    .timer_irq(TIMER_IRQ)
  );

// AHBLite GPIO	
  AHBGPIO uAHBGPIO(
    .HCLK(HCLK),
    .HRESETn(HRESETn),
    .HADDR(HADDR[31:0]),
    .HWRITE(HWRITE),
    .HWDATA(HWDATA[31:0]),
    .HTRANS(HTRANS),
    .HSEL(HSEL_GPIO),
    .HREADY(HREADY),
    .GPIOIN({8'b00000000,sw[7:0]}),
    .HREADYOUT(HREADYOUT_GPIO),
    .HRDATA(HRDATA_GPIO[31:0]),
    .GPIOOUT(LED[7:0])
  );
	
endmodule