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module AHBLITE_SYS(
	//CLOCKS & RESET
	input		wire				CLK,
	input		wire				RESET, 
	
	//TO BOARD LEDs
		output 	wire	[7:0] 	LED,
    	output 	wire			LOCKUP,
	
	//TOWARDS MEMORY
	inout  	wire	[15:0] 	MemDB,
	output 	wire	[23:1] 	MemAdr,
	output 	wire				RamCEn,
	output 	wire				RamWEn,
	output 	wire				RamOEn,
	output 	wire				RamUBn,
	output 	wire				RamLBn,
	output 	wire				RamCRE,
	output 	wire				RamADVn,
	output 	wire				RamCLK,
	input 	wire				RamWait,
	
	//TO UART
	input 	wire				RsRx,
	output 	wire				RsTx
);
 
//AHB-LITE SIGNALS 
//Gloal Signals
wire 				HCLK;
wire 				HRESETn;
//Address, Control & Write Data Signals
wire [31:0]		HADDR;
wire [31:0]		HWDATA;
wire 				HWRITE;
wire [1:0] 		HTRANS;
wire [2:0] 		HBURST;
wire 				HMASTLOCK;
wire [3:0] 		HPROT;
wire [2:0] 		HSIZE;
//Transfer Response & Read Data Signals
wire [31:0] 	HRDATA;
wire 				HRESP;
wire 				HREADY;

//SELECT SIGNALS
wire [3:0] 		MUX_SEL;

wire 				HSEL_MEM;
wire 				HSEL_LED;
wire 				HSEL_UART;

//SLAVE READ DATA
wire [31:0] 	HRDATA_MEM;
wire [31:0] 	HRDATA_LED;
wire [31:0] 	HRDATA_UART;

//SLAVE HREADYOUT
wire 				HREADYOUT_MEM;
wire 				HREADYOUT_LED;
wire 				HREADYOUT_UART;

//CM0-DS Sideband signals
wire 				LOCKUP;
wire 				TXEV;
wire 				SLEEPING;
wire [15:0]		IRQ;
  
//Map signal with the memory controller
wire[26:1] MemAdr_SRAMCTRL;  

//Map signal with the memory controller
assign MemAdr = MemAdr_SRAMCTRL[23:1];
  
//SYSTEM GENERATES NO ERROR RESPONSE
assign 			HRESP = 1'b0;

//CM0-DS INTERRUPT SIGNALS  
assign 			IRQ = {16'b0000_0000_0000_0000};


assign 			HRESETn = ~ RESET;

// Clock divider, divide the frequency by two, hence less time constraint 
reg clk_div=0;

  always @(posedge CLK)
  begin
    clk_div=~clk_div;
  end

// A global clock buffer
  BUFG BUFG_CLK (
      .O(HCLK), 		// 1-bit output: Clock buffer output
      .I(clk_div)  	// 1-bit input: Clock buffer input
  );


                 

//AHBLite MASTER --> CM0-DS

CORTEXM0DS u_cortexm0ds (
	//Global Signals
	.HCLK        (HCLK),
	.HRESETn     (HRESETn),
	//Address, Control & Write Data	
	.HADDR       (HADDR[31:0]),
	.HBURST      (HBURST[2:0]),
	.HMASTLOCK   (HMASTLOCK),
	.HPROT       (HPROT[3:0]),
	.HSIZE       (HSIZE[2:0]),
	.HTRANS      (HTRANS[1:0]),
	.HWDATA      (HWDATA[31:0]),
	.HWRITE      (HWRITE),
	//Transfer Response & Read Data	
	.HRDATA      (HRDATA[31:0]),			
	.HREADY      (HREADY),					
	.HRESP       (HRESP),					

	//CM0 Sideband Signals
	.NMI         (1'b0),
	.IRQ         (IRQ[15:0]),
	.TXEV        (),
	.RXEV        (1'b0),
	.LOCKUP      (LOCKUP),
	.SYSRESETREQ (),
	.SLEEPING    ()
);

//Address Decoder 

AHBDCD uAHBDCD (
	.HADDR(HADDR[31:0]),
	 
	.HSEL_S0(HSEL_MEM),
	.HSEL_S1(HSEL_LED),
	.HSEL_S2(HSEL_UART),
	.HSEL_S3(),
	.HSEL_S4(),
	.HSEL_S5(),
	.HSEL_S6(),
	.HSEL_S7(),
	.HSEL_S8(),
	.HSEL_S9(),
	.HSEL_NOMAP(HSEL_NOMAP),
	 
	.MUX_SEL(MUX_SEL[3:0])
);

//Slave to Master Mulitplexor

AHBMUX uAHBMUX (
	.HCLK(HCLK),
	.HRESETn(HRESETn),
	.MUX_SEL(MUX_SEL[3:0]),
	 
	.HRDATA_S0(HRDATA_MEM),
	.HRDATA_S1(HRDATA_LED),
	.HRDATA_S2(HRDATA_UART),
	.HRDATA_S3(),
	.HRDATA_S4(),
	.HRDATA_S5(),
	.HRDATA_S6(),
	.HRDATA_S7(),
	.HRDATA_S8(),
	.HRDATA_S9(),
	.HRDATA_NOMAP(32'hDEADBEEF),
	 
	.HREADYOUT_S0(HREADYOUT_MEM),
	.HREADYOUT_S1(HREADYOUT_LED),
	.HREADYOUT_S2(HREADYOUT_UART),
	.HREADYOUT_S3(1'b1),
	.HREADYOUT_S4(1'b1),
	.HREADYOUT_S5(1'b1),
	.HREADYOUT_S6(1'b1),
	.HREADYOUT_S7(1'b1),
	.HREADYOUT_S8(1'b1),
	.HREADYOUT_S9(1'b1),
	.HREADYOUT_NOMAP(1'b1),
    
	.HRDATA(HRDATA[31:0]),
	.HREADY(HREADY)
);
// AHBLite Peripherals

// AHBLite Memory Controller  
AHB2SRAMFLSH uAHB2SRAMFLSH (
	.HCLK(HCLK),
	.HRESETn(HRESETn), 
	.HADDR(HADDR[31:0]), 
	.HSEL(HSEL_MEM),
	.HREADY(HREADY),
	.HSIZE(HSIZE[2:0]), 
	.HTRANS(HTRANS[1:0]), 
	.HWDATA(HWDATA[31:0]), 
	.HWRITE(HWRITE), 
	.HRDATA(HRDATA_MEM[31:0]), 
	.HREADYOUT(HREADYOUT_MEM), 
	
	.MemDB(MemDB), 
	.MemAdr(MemAdr_SRAMCTRL), 
	.RamCS(RamCEn), 
	.MemWR(RamWEn), 
	.MemOE(RamOEn), 
	.RamUB(RamUBn), 
	.RamLB(RamLBn), 
	.RamCre(RamCRE), 
	.RamAdv(RamADVn), 
	.RamClk(RamCLK), 
	.RamWait(RamWait)
);


AHBUART uAHBUART(
	.HCLK(HCLK),
	.HRESETn(HRESETn),
	.HADDR(HADDR[31:0]),
	.HTRANS(HTRANS[1:0]),
	.HWDATA(HWDATA[31:0]),
	.HWRITE(HWRITE),
	.HREADY(HREADY),
	.HREADYOUT(HREADYOUT_UART),
	.HRDATA(HRDATA_UART[31:0]),
	.HSEL(HSEL_UART),
	
	.RsRx(RsRx),
	.RsTx(RsTx)
//	.uart_irq(UART_IRQ)
    );
    
//AHBLite Slave 
    AHB2LED uAHB2LED (
    	//AHBLITE Signals
    	.HSEL(HSEL_LED),
    	.HCLK(HCLK), 
    	.HRESETn(HRESETn), 
    	.HREADY(HREADY),     
    	.HADDR(HADDR),
    	.HTRANS(HTRANS[1:0]), 
    	.HWRITE(HWRITE),
    	.HSIZE(HSIZE),
    	.HWDATA(HWDATA[31:0]), 
    	
    	.HRDATA(HRDATA_LED), 
    	.HREADYOUT(HREADYOUT_LED),
    	//Sideband Signals
    	.LED(LED)
    );

endmodule