f Command: %s 1870* planAhead2: &open_checkpoint AHBLITE_SYS_routed.dcp2default:defaultZ12-2866 ] -Analyzing %s Unisim elements for replacement 17*netlist2 342default:defaultZ29-17 a 2Unisim Transformation completed in %s CPU seconds 28*netlist2 02default:defaultZ29-28  Netlist '%s' is not ideal for floorplanning, since the cellview '%s' defined in file '%s' contains large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. 43*netlist2 AHBLITE_SYS2default:default2$ cortexm0ds_logic2default:default2# AHBLITE_SYS.edf2default:defaultZ29-43 o Netlist was created with %s %s291*project2 Vivado2default:default2 2013.42default:defaultZ1-479  Loading clock regions from %s 13*device2d PC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockRegion.xml2default:defaultZ21-13  Loading clock buffers from %s 11*device2e QC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/ClockBuffers.xml2default:defaultZ21-11  &Loading clock placement rules from %s 318*place2Y EC:/Xilinx/Vivado/2013.4/data/parts/xilinx/artix7/ClockPlacerRules.xml2default:defaultZ30-318  )Loading package pin functions from %s... 17*device2U AC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/PinFunctions.xml2default:defaultZ21-17  Loading package from %s 16*device2g SC:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/artix7/xc7a100t/csg324/Package.xml2default:defaultZ21-16  Loading io standards from %s 15*device2V BC:/Xilinx/Vivado/2013.4/data\./parts/xilinx/artix7/IOStandards.xml2default:defaultZ21-15  +Loading device configuration modes from %s 14*device2T @C:/Xilinx/Vivado/2013.4/data\parts/xilinx/artix7/ConfigModes.xml2default:defaultZ21-14  Parsing XDC File [%s] 179* designutils2 C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/P6/Lab Part2/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-6680-/dcp/AHBLITE_SYS.xdc2default:defaultZ20-179  Finished Parsing XDC File [%s] 178* designutils2 C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/P6/Lab Part2/FPGA/Nexys4/Nexys4.runs/impl_1/.Xil/Vivado-6680-/dcp/AHBLITE_SYS.xdc2default:defaultZ20-178 6 Reading XDEF placement. 206* designutilsZ20-206 4 Reading XDEF routing. 207* designutilsZ20-207  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2$ Read XDEF File: 2default:default2 00:00:002default:default2 00:00:00.1832default:default2 860.6842default:default2 0.6022default:defaultZ17-268 3 Restoring placement. 754* designutilsZ20-754  ORestored %s out of %s XDEF sites from archive | CPU: %s secs | Memory: %s MB | 403* designutils2 9412default:default2 9412default:default2 0.0000002default:default2 0.0000002default:defaultZ20-403 C Pushed %s inverter(s). 98*opt2 02default:defaultZ31-138 | MSuccessfully populated the BRAM INIT strings from the following elf files: %s96*memdata2 2default:defaultZ28-144  !Unisim Transformation Summary: %s111*project2  A total of 32 instances were transformed. RAM256X1S => RAM256X1S (RAMS64E, RAMS64E, RAMS64E, RAMS64E, MUXF7, MUXF7, MUXF8): 32 instances 2default:defaultZ1-111 Y $Checkpoint was created with build %s293*project2 3535832default:defaultZ1-484  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2% open_checkpoint: 2default:default2 00:00:182default:default2 00:00:192default:default2 864.0312default:default2 680.4612default:defaultZ17-268  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2" Implementation2default:default2 xc7a100t2default:defaultZ17-347  0Got license for feature '%s' and/or device '%s' 310*common2" Implementation2default:default2 xc7a100t2default:defaultZ17-349 o ,Running DRC as a precondition to command %s 1349* planAhead2# write_bitstream2default:defaultZ12-1349 G Running DRC with %s threads 24*drc2 22default:defaultZ23-27 ] DRC finished with %s 1905* planAhead2( 0 Errors, 1 Warnings2default:defaultZ12-3199 ` BPlease refer to the DRC report (report_drc) for more information. 1906* planAheadZ12-3200 6 Loading data files... 1271* designutilsZ12-1165 5 Loading site data... 1273* designutilsZ12-1167 6 Loading route data... 1272* designutilsZ12-1166 6 Processing options... 1362* designutilsZ12-1514 3 Creating bitmap... 1249* designutilsZ12-1141 . Creating bitstream... 7* bitstreamZ40-7 Y Writing bitstream %s... 11* bitstream2% ./AHBLITE_SYS.bit2default:defaultZ40-11 = Bitgen Completed Successfully. 1606* planAheadZ12-1842  WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 120*projectZ1-120  '%s' has been successfully sent to Xilinx on %s. For additional details about this file, please refer to the Webtalk help file at %s. 186*common2 C:/Users/karshi01/Desktop/Workshop/USB/Full Material - V5/P6/Lab Part2/FPGA/Nexys4/Nexys4.runs/impl_1/usage_statistics_webtalk.xml2default:default2, Sun Apr 13 14:31:32 20142default:default2I 5C:/Xilinx/Vivado/2013.4/doc/webtalk_introduction.html2default:defaultZ17-186 Q Releasing license: %s 83*common2" Implementation2default:defaultZ17-83  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2% write_bitstream: 2default:default2 00:00:272default:default2 00:00:292default:default2 1221.6522default:default2 357.6212default:defaultZ17-268  End Record