ncverilog: 15.10-s002: (c) Copyright 1995-2015 Cadence Design Systems, Inc. TOOL: ncverilog 15.10-s002: Started on Sep 30, 2016 at 14:09:31 BST ncverilog -sv +gui +ncaccess+r -sv ../TestBench/nexys4_wrapper_stim.sv -y ../SVerilogSource +libext+.sv -y ../VerilogSource +libext+.v -s file: ../TestBench/nexys4_wrapper_stim.sv module worklib.nexys4_wrapper_stim:sv errors: 0, warnings: 0 file: ../SVerilogSource/nexys4_wrapper.sv module SVerilogSource.nexys4_wrapper:sv errors: 0, warnings: 0 file: ../SVerilogSource/ahb_system.sv module SVerilogSource.ahb_system:sv errors: 0, warnings: 0 file: ../SVerilogSource/ahb_interconnect.sv module SVerilogSource.ahb_interconnect:sv errors: 0, warnings: 0 file: ../SVerilogSource/ahb_mem.sv module SVerilogSource.ahb_mem:sv errors: 0, warnings: 0 file: ../SVerilogSource/ahb_leds.sv module SVerilogSource.ahb_leds:sv errors: 0, warnings: 0 file: ../SVerilogSource/ahb_switches.sv module SVerilogSource.ahb_switches:sv errors: 0, warnings: 0 file: ../VerilogSource/CORTEXM0DS.v module VerilogSource.CORTEXM0DS:v errors: 0, warnings: 0 file: ../VerilogSource/cortexm0ds_logic.v module VerilogSource.cortexm0ds_logic:v errors: 0, warnings: 0 Caching library 'worklib' ....... Done Caching library 'SVerilogSource' ....... Done Caching library 'VerilogSource' ....... Done Elaborating the design hierarchy: ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics. Building instance overlay tables: .................... Done Generating native compiled code: SVerilogSource.ahb_interconnect:sv <0x1148b3c9> streams: 4, words: 2441 SVerilogSource.ahb_leds:sv <0x5ced2810> streams: 13, words: 5335 SVerilogSource.ahb_mem:sv <0x1bdd072c> streams: 16, words: 7653 SVerilogSource.ahb_switches:sv <0x16352c24> streams: 8, words: 2899 SVerilogSource.ahb_system:sv <0x3ec4b7b1> streams: 2, words: 673 SVerilogSource.nexys4_wrapper:sv <0x5c45bfdf> streams: 8, words: 1696 VerilogSource.CORTEXM0DS:v <0x38e3403c> streams: 6, words: 846 VerilogSource.cortexm0ds_logic:v <0x0d3909f6> streams: 2204, words: 676078 worklib.nexys4_wrapper_stim:sv <0x21413713> streams: 2, words: 3808 Building instance specific data structures. Loading native compiled code: .................... Done Design hierarchy summary: Instances Unique Modules: 9 9 Registers: 886 886 Scalar wires: 11131 - Expanded wires: 119 5 Vectored wires: 26 - Always blocks: 852 852 Initial blocks: 2 2 Cont. assignments: 957 11119 Pseudo assignments: 1 1 Writing initial simulation snapshot: worklib.nexys4_wrapper_stim:sv ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics. ncsim> ncsim> source /opt/cad/soft/cadence/incisiv/tools/inca/files/ncsimrc ncsim> ------------------------------------- Relinquished control to SimVision... # Restoring simulation environment... ncsim> input -quiet .reinvoke.sim ncsim> file delete .reinvoke.sim ncsim> database -open waves -into waves.shm -default Created default SHM database waves ncsim> probe -create -shm nexys4_wrapper_stim.Clock nexys4_wrapper_stim.LEDs nexys4_wrapper_stim.Status_Green nexys4_wrapper_stim.Status_Red nexys4_wrapper_stim.Switches nexys4_wrapper_stim.nReset Created probe 1 ncsim> run LED Update: 42405 @ 1180 LED Update: 0 @ 2742 LED Update: 257 @ 3732 LED Update: 0 @ 5228 LED Update: 257 @ 6218 LED Update: 0 @ 7714 LED Update: 257 @ 8704 LED Update: 0 @ 10200 LED Update: 257 @ 11190 LED Update: 0 @ 12686 LED Update: 257 @ 13676 LED Update: 0 @ 15172 LED Update: 257 @ 16162 LED Update: 0 @ 17658 LED Update: 257 @ 18648 LED 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