// Example code for an M0 AHBLite System // Iain McNally // ECS, University of Soutampton module ahb_system( input HCLK, HRESETn, input [15:0] Switches, output [15:0] LEDs, output LOCKUP ); // Global & Master AHB Signals wire [31:0] HADDR, HWDATA, HRDATA; wire [1:0] HTRANS; wire [2:0] HSIZE, HBURST; wire [3:0] HPROT; wire HWRITE, HMASTLOCK, HRESP, HREADY; // Per-Slave AHB Signals wire HSEL_SW, HSEL_MEM, HSEL_LED; wire [31:0] HRDATA_SW, HRDATA_MEM, HRDATA_LED; wire HREADYOUT_SW, HREADYOUT_MEM, HREADYOUT_LED; // Non-AHB M0 Signals wire TXEV, RXEV, SLEEPING, SYSRESETREQ, NMI; wire [15:0] IRQ; // Set this to zero because simple slaves do not generate errors assign HRESP = '0; // Set all interrupt and event inputs to zero (unused in this design) assign NMI = '0; assign IRQ = {16'b0000_0000_0000_0000}; assign RXEV = '0; // Coretex M0 DesignStart is AHB Master CORTEXM0DS m0_1 ( // AHB Signals .HCLK, .HRESETn, .HADDR, .HBURST, .HMASTLOCK, .HPROT, .HSIZE, .HTRANS, .HWDATA, .HWRITE, .HRDATA, .HREADY, .HRESP, // Non-AHB Signals .NMI, .IRQ, .TXEV, .RXEV, .LOCKUP, .SYSRESETREQ, .SLEEPING ); // AHB interconnect including address decoder, register and multiplexer ahb_interconnect interconnect_1 ( .HCLK, .HRESETn, .HADDR, .HRDATA, .HREADY, .HSEL_SIGNALS({HSEL_SW,HSEL_LED,HSEL_MEM}), .HRDATA_SIGNALS({HRDATA_SW,HRDATA_LED,HRDATA_MEM}), .HREADYOUT_SIGNALS({HREADYOUT_SW,HREADYOUT_LED,HREADYOUT_MEM}) ); // AHBLite Slaves ahb_mem mem_1 ( .HCLK, .HRESETn, .HADDR, .HWDATA, .HSIZE, .HTRANS, .HWRITE, .HREADY, .HSEL(HSEL_MEM), .HRDATA(HRDATA_MEM), .HREADYOUT(HREADYOUT_MEM) ); ahb_leds leds_1 ( .HCLK, .HRESETn, .HADDR, .HWDATA, .HSIZE, .HTRANS, .HWRITE, .HREADY, .HSEL(HSEL_LED), .HRDATA(HRDATA_LED), .HREADYOUT(HREADYOUT_LED), .LEDs(LEDs) ); ahb_switches switches_1 ( .HCLK, .HRESETn, .HADDR, .HWDATA, .HSIZE, .HTRANS, .HWRITE, .HREADY, .HSEL(HSEL_SW), .HRDATA(HRDATA_SW), .HREADYOUT(HREADYOUT_SW), .Switches(Switches) ); endmodule