Verilog Simulation with Verilog-XL and ModelSim

The Verilog-XL digital simulator will simulate the behaviour of a digital circuit provided that a Verilog HDL model file exists for that circuit. The creation of such a model file is described elsewhere; this page describes the simulation process assuming that the model already exists.

Because of it's complexity, Verilog is best described by example. We will consider the simulation of a number of simple circuits starting with an RS flip-flop:

The Verilog HDL model file for this circuit is rs_flipflop.v.

Simulation 1

A Very Simple Stimulus File

The following file, rs_flipflop_stim1.v, is a simple stimulus file for the RS flip-flop:

Major Features

For a more detailed description of the Verilog constructs used, see the cdsdoc on-line manual.

Running the Simulator

Ensure that you are logged in to a machine which runs verilog1.

Type the following at the unix command prompt:

or

The simulator output is in the form of a value for Time, notR, notS and Q printed each time that one of the inputs or outputs changes. It should look something like this:

Try both simulation commands and check that you get the same result with each.

Simulation 2

More Advanced Monitoring

A new stimulus file, rs_flipflop_stim2.v, illustrates some of the more advanced monitoring features available using Verilog:

....
module rs_flipflop_stim2;
   ....
   ....
      #1000
         $display("\n                    Simulation complete\n");
         $stop;
         $finish;
      end

   // probe information
   //  - generic verilog commands

   initial
      begin
         $display("                Time     Inputs    Outputs");
         $display("                       notR  notS     Q");
         $display("                ====   ==========  =======");
         $monitor($time,"     %b    %b       %b", notR, notS, Q);
      end

   // probe information
   //  - Verilog-XL specific commands

   initial
      begin
         $timeformat(-10);
	 $gr_position( "waves", 0,0,600,200);
	 $gr_waves( "not R", notR,
                    "not S", notS,
                    "Q",     Q,
                    "not Q", rs_instance1.not_q);
      end

   // probe information
   //  - ModelSim specific commands

   //VSIM COMMAND: view wave -x 0 -y 300 -width 800 -height 300
   //VSIM COMMAND: add wave -label "not R" notR -label "not S" notS
   //VSIM COMMAND: add wave -label "Q" Q
   //VSIM COMMAND: add wave -label "not Q" rs_instance1/not_q
   //VSIM COMMAND: run -all

endmodule

Major Features

For a more detailed description of the Verilog constructs used, see the cdsdoc on-line manual.

Running the Simulator

Type the following at the unix command prompt:

or

Here we use different versions of the simulators; "verilog_xl" contains support for the Verilog-XL graphics tasks while "modelsim" runs the graphical version of the ModelSim simulator allowing multiple windows to be opened for display of graphical information.

Either simulator should provide this formatted text output:

                Time     Inputs    Outputs
                       notR  notS     Q
                ====   ==========  =======
                   0     1    1       x
                1000     0    1       0
                2000     1    1       0
                3000     1    0       1
                4000     1    1       1
                5000     0    1       0
                6000     1    1       0

                    Simulation complete

and a graphical waveform window which will depend on the simulator:

Verilog-XL

ModelSim

To illustrate further functionality we will consider the simulation of a simple up/down counter:

The Verilog HDL model file for this circuit is up_down_count.v.

Simulation 3

Stimulus File

The following file, up_down_count_stim.v, is a stimulus file for the up/down counter:

Major Features

For a more detailed description of the Verilog constructs used, see the cdsdoc on-line manual.

Running the Simulator

Type the following at the unix command prompt:

or

Verilog-XL

ModelSim

The ModelSim windows are less sophisticated (there is no link between the wave window and the list window) and hence need rather less explanation:

Summary of Interfaces

In this lab you should have seen Verilog-XL with its lightweight interface and ModelSim with its more modern graphical user interface (GUI).

There is a third interface available, a modern GUI for Verilog-XL. This can be invoked using the "verilog +gui" command. Unfortunately this GUI doesn't support the REGS window which turns out to be very useful for processor development and visualisation.

Both modern GUIs support an interactive debugging style that you may be familiar with from programming. If you want to experiment with this, the ModelSim version is probably better integrated.

Additional Documentation

All Verilog documentation is available on-line via cdsdoc. Type the following at the unix command prompt in order to invoke cdsdoc:

On-line manuals of particular interest to this tutorial are:

Verilog Capable Machines

1The verilog program runs on the ISS Solaris sever (ironwood) and on the ECS CAD server (salvador). If you are logged into one of these machines you can check the availability of verilog by typing:

If you get a "verilog_xl: Command not found." message you should check your account configuration.

If you need only the non-graphics implementation of the simulator you can run verilog on a verilog capable machine when remotely logged in from any other machine using telnet.
If you need graphical output, then you must be sitting at a machine with X-windows running and correctly configured. The best way to be sure of X-windows capability is to sit at a verilog capable machine.

Iain McNally

22-12-2003