Verilog Simulation with Xcelium and ModelSim

The Xcelium digital simulator will simulate the behaviour of a digital circuit provided that a Verilog HDL model file exists for that circuit. The creation of such a model file is described elsewhere; this page describes the simulation process assuming that the model already exists.

Because of it's complexity, Verilog is best described by example. We will consider the simulation of a number of simple circuits starting with an RS flip-flop:

The Verilog HDL model file for this circuit is rs_flipflop.v.

A Very Simple Stimulus File

The following file, rs_flipflop_stim1.v, is a simple stimulus file for the RS flip-flop:

Major Features

For a more detailed description of the Verilog constructs used, see the Cadence Help on-line manual.

Running the Simulator

Download the verilog source files into a suitable directory (e.g. ~/design/verilog/lab/simulation) and type the following at the unix command prompt:

    verilog  rs_flipflop_stim1.v  rs_flipflop.v
or 
    xmverilog  rs_flipflop_stim1.v  rs_flipflop.v
or 
    modelsim_batch  rs_flipflop_stim1.v  rs_flipflop.v

The simulator output is in the form of a value for Time, notR, notS and Q printed each time that one of the inputs or outputs changes. It should look something like this:

                Time     Inputs    Outputs
                       notR  notS     Q
                ====   ==========  =======
                   0     1    1       x
                1000     0    1       0
                2000     1    1       0
                3000     1    0       1
                4000     1    1       1
                5000     0    1       0
                6000     1    1       0

                    Simulation complete

Try all three simulation commands and check that you get the same result with each.

Automatic Verification

Although a simple stimulus file exercises the design and allows us to see the results, it does not tell us if the design is working. A new version of the stimulus file, rs_flipflop_stim2.v, adds automatic verification and tells us if the design is working or not:

Major Features

Re-simulate

Download the new stimulus file and execute the simulation command: 

    verilog  rs_flipflop_stim2.v  rs_flipflop.v

When an error is flagged during automatic verification there are two possible sources:

  1. there is a problem with the design not meeting the specification
  2. there is a problem with the tests performed

In fact there is a mistake in the rs_flipflop_stim2.v file. Identify and correct this mistake and then re-run the simulation.

Displaying Waveforms

The two simulators used so far, Xcelium and ModelSim, each provide a graphical user interface (GUI) for waveform display. This lab will cover the use of the SimVision GUI for Xcelium and the ModelSim GUI. The Verilog-XL GUI is documented elsewhere.

Xcelium SimVision GUI

Run the command 

    xmverilog  +gui +access+r  rs_flipflop_stim1.v  rs_flipflop.v

The verilog files rs_flipflop_stim1.v and rs_flipflop.v are first checked for syntax errors then converted into an internal format and finally linked together ready for simulation. This process is known as compilation and elaboration.

If the compilation and elaboration is successful, the +gui option causes the SimVision GUI to be opened to control the final simulation stage and to view the resulting waveforms. Note that the +access+r option ensures that SimVision is granted read access to the simulation database. Without this access permission, no waveforms could be displayed.

If all goes well you should find you are presented with two new windows, the SimVision Console and the SimVision Design Browser:

Select the rs_flip_flop_stim instance:

Select all three signals in the Signal/Variable section of the window:

Click the waves icon, , to send the selected signals to a waveform viewer window.

Click the play icon, , to run the simulation to the first breakpoint (in this case the terminating $finish; command) and then click the full view icon, , to show the complete waveforms:

Viewing internal nodes

Expand the rs_flipflop_stim instance in the browser window by selecting the sign from . Then select the newly visible rs_instance1 instance and then the not_q signal within that instance:

Click the waves icon, , to send the selected signal to the waveform window. At this stage no waveform is visble for not_q signal since it was not probed when the simulation was run:

Click the rewind icon and then the play and full view icons, , to re-run the simulation:

To print the resulting waveform invoke the Print Window dialogue from the Waveform window File menu: 

    File -> Print Window...

      Print
        Printer
          Comand:     [ lpr -l -P <printername>  ]
        Print Paper
          Paper Size: [ A4 (210mm x 297mm)    ] 
      OK

To exit the simulator select Exit SimVision from the File menu:

    File -> Exit SimVision

SimVision command scripts

Where you wish to run simulations repeatedly (e.g. during development) or offer another user the chance to reproduce your simulations, a SimVision command script will save a lot of time.

The following file, rs_flipflop.tcl, is a simple SimVision script file for the RS flip-flop:

Download the rs_flipflop.tcl command script and re-run the simulation including the +tcl option: 

    xmverilog  +gui +access+r  rs_flipflop_stim1.v  rs_flipflop.v  +tcl+rs_flipflop.tcl

Then run the simulation ( ). The result is as before except that the waveform window has the name given to it in the command script:

If you forget to use the +tcl option when you run the simulation, you can load the command script once SimVision is running: 

    File -> Source Command Script...

      Source Command Script
      
        Filename:         [ rs_flipflop.tcl               ]

        Send commands to: [ simulator Console (XM-Sim)  - ]
	
      OK
this facility is very useful when developing command scripts.

You can write your own command script provided that you understand the naming convention for the signals. Each signal name is qualified by it's scope (i.e. the hierarchical name of the module in which the signal exists). Thus "rs_flipflop_stim.rs_instance1.not_q" refers to a signal named "not_q" within a module with instance name "rs_instance1" within the top level module "rs_flipflop_stim".

Note that signals which connect to module ports (inputs and outputs) can have multiple names since they have different names in the parent and child scope. Thus in this example, "rs_flipflop_stim.rs_instance1.q" is an alias for the signal "rs_flipflop_stim.Q".

ModelSim GUI

Edit the stimulus file "rs_flipflop_stim1.v" and add a statement "$stop;" just before the "$finish;" statement (this will prevent the modelsim simulation from terminating before you have looked at the waveforms).

Run the command 

    modelsim  rs_flipflop_stim1.v  rs_flipflop.v

The behaviour of ModelSim is very similar to that of Xcelium in that it compiles the modules and then opens the the ModelSim GUI "Main Window":

As with Xcelium, the display of waveforms may be controlled either via selecting instances and signals and sending them to a waveform window or via a command script.

The following file, rs_flipflop.vsim, is a simple ModelSim script file for the RS flip-flop:

Download the rs_flipflop.vsim command script and then execute it by typing "source rs_flipflop.vsim" at the "VSIM >" prompt in the ModelSim main window.

Then run the simulation either by typing "run -all" at the "VSIM >" prompt or by selecting the run -all icon, .

In order to see the full waveforms you will need to select Zoom -> Zoom Full from the pull down menus of the wave window or select the zoom full icon, .

The resulting waveform window should look something like this:

To print the waveform invoke the Print Postscript dialogue from the Waveform window File menu: 

    File -> Print Postscript...

      Write Postscript
        Printer
          [x] Printer Command: [ lpr -P <printername>      ]
      [OK]

If you have problems printing you may need to check that the page size is correctly set up File -> Page Setup... (either "A4 Sheet" or "A4 small sheet" should work).

You can then terminate the simulation by typing the following command in the main ModelSim window:

    quit

To illustrate further functionality we will consider the simulation of a simple up/down counter:

The Verilog HDL model file for this circuit is up_down_count.v.

Stimulus File

The following file, up_down_count_stim.v, is a stimulus file for the up/down counter:

Major Features

Here an "always begin end" construct is used to create a repetitive clock with a cycle time of 1000 units (1ns per unit). The "initial begin end" construct is used for changes in the stimulus signals which don't repeat.

The status interpretation section introduces two new concepts; the first is the declaration of a function and the second is the interpretation of a multibit value as a string. The result is a simulation that not only reports the state of the system but is also able to interpret the results it gets - it knows whether the counter is counting up or down and tells us so.

Note that the "wire [6*8:1]" declaration is creating a bus with enough bits to store a 6 character string where each charater is an 8 bit ASCII value.

SimVision Command Script

The following file, up_down_count.tcl, is a SimVision script file for the up/down counter:

Xcelium Simulation

Execute the simulation command: 
    xmverilog  +gui +access+r  up_down_count_stim.v  up_down_count.v  +tcl+up_down_count.tcl

ModelSim Command Script

The following file, up_down_count.vsim, is a ModelSim script file for the up/down counter:

ModelSim Simulation

Execute the simulation command: 
    modelsim  up_down_count_stim.v  up_down_count.v

Then source the command script up_down_count.vsim.

Overview of Simulation Tools

In this lab you should have seen the Verilog-XL simulator in text only (batch) mode and the Xcelium and ModelSim simulators in GUI and batch mode versions.

N.B. In general, GUI simulations are used in development, while batch mode simulations are used for verification against known functionality. For example, when students submit designs for marking, a batch mode simulation will be run and should give a simple pass/fail result without having to study waveforms.

Additional Documentation

All Verilog documentation is available on-line via Cadence Help. Type the following at the unix command prompt in order to invoke Cadence Help:

On-line manuals of particular interest to this tutorial are:

Iain McNally

8-10-2023