// Example code for an M0 AHBLite System
//  Iain McNally
//  ECS, University of Soutampton
//
// This module is incomplete model of an AHB-Lite Slave containing four read/write registers
//   you should fill missing code where you see "** add code here **" below
//
// Number of addressable locations : 4
// Size of each addressable location : 32 bits
// Supported transfer sizes : Word
// Alignment of base address : Word aligned
//
// Address map :
//   Base addess + 0 : 
//     Read ouput port (oA) register
//     Write ouput port (oA) register
//   Base addess + 4 : 
//     Read ouput port (oB) register
//     Write ouput port (oB) register
//   Base addess + 8 : 
//     Read ouput port (oC) register
//     Write ouput port (oC) register
//   Base addess + 12 : 
//     Read ouput port (oD) register
//     Write ouput port (oD) register


module ahb_custom_interface(

  // AHB Global Signals
  input HCLK,
  input HRESETn,

  // AHB Signals from Master to Slave
  input [31:0] HADDR, // With this interface only HADDR[3:2] is used (other bits are ignored)
  input [31:0] HWDATA,
  input [2:0] HSIZE,
  input [1:0] HTRANS,
  input HWRITE,
  input HREADY,
  input HSEL,

  // AHB Signals from Slave to Master
  output logic [31:0] HRDATA,
  output HREADYOUT,

  //Non-AHB Signals
  output logic [31:0] oA,
  output logic [31:0] oB,
  output logic [31:0] oC,
  output logic [31:0] oD

);

timeunit 1ns;
timeprecision 100ps;

  // AHB transfer codes needed in this module
  localparam No_Transfer = 2'b0;

  //control signals are stored in registers
  logic write_enable, read_enable;
  logic [1:0] word_address;
 
  //Generate the control signals in the address phase
  
    // *******************
    // ** add code here **
    // *******************

  //Act on control signals in the data phase

  // write

    // *******************
    // ** add code here **
    // *******************
     
  // read

    // *******************
    // ** add code here **
    // *******************
     
  //Transfer Response
  assign HREADYOUT = '1; //Single cycle Write & Read. Zero Wait state operations


endmodule