module arm_soc_stim();
     
timeunit 1ns;
timeprecision 100ps;

  logic HRESETn, HCLK; 
  logic [15:0] Switches;
  wire [15:0] DataOut;
  wire DataValid;
  wire LOCKUP;
  wire [31:0] iPort, oPort;

  assign iPort = { 16'd0, Switches }; // We'll simulate just 16 switches
  assign DataOut = oPort[15:0]; // We'll simulate just 16 LEDs
  assign DataValid = (oPort != -1);
  
  arm_soc dut(.HCLK, .HRESETn, .oPort, .iPort, .LOCKUP);

  always
    begin
           HCLK = 0;
      #5ns HCLK = 1;
      #10ns HCLK = 0;
      #5ns HCLK = 0;
    end

  initial
    begin
            HRESETn = 0;
            Switches = 1;
      #10.0ns HRESETn = 1;
            
      #10us Switches = 0;

      #10us Switches = 1;

      #10us Switches = 2;

      #10us Switches = 3;

      #10us Switches = 4;

      #20us Switches = 5;

      #20us Switches = 6;

      #20us Switches = 7;

      #20us Switches = 8;

      #30us Switches = 15;

      #40us Switches = 12;

      #50us $stop;
            $finish;
    end
       
endmodule