Magic - Design Rule Checking using Cadence Assura (via Cadence Virtuoso)

Cadence and Magic use different file formats for the storage of design data.
Interchange is possible via a common GDS2 stream format.

Procedure

• go to magic directory e.g.

    cadteaching7<~>$ cd ~/design/magic/tsmc180/cell_lib
  

• translate Magic file to Cadence format

    cadteaching7<~/design/magic/tsmc180/cell_lib>$ do_tsmc180_cellin <cellname>
  

  cell cellname (in file cellname.mag) and all sub-cells will be translated.

The Magic layout editor supports simple on-line DRC.
The Cadence Virtuso layout editor supports the Assura DRC post-processor.

Magic designs must pass the more stringent Assura DRC before they will be accepted for fabrication.

Procedure

• Change to directory containing Cadence files

    cadteaching7<~/design/magic/tsmc180/cell_lib>$ cd ~/design/cadence/tsmc180/cell_lib
  

• Start Cadence Virtuoso

    cadteaching7<~/design/cadence/tsmc180/cell_lib>$ virtuoso
  

• Use the library manager for library, cell and cellview manipulation

    Tools -> Library Manager...
  

  Within the library browser the left hand mouse button is used for navigating around the library structure while the right hand mouse button provides access to the commands used to manipulate the libraries, cells and cellviews.

  • Open the imported design for edit

    Use the mouse to select Library: cell_lib, Cell: <cellname> and View: layout then invoke the open command -

      File -> Open...
    

• Perform DRC based on files in the assura_dir run directory

    Assura -> Run DRC...
  
      Run Assura DRC
        Run Directory        [ assura_dir              ]
        Rules File           [ assura_dir/assura.drc   ]
        Run Directory        [ assura_dir/assua.rsf    ]
      OK
  

• Once the DRC run is complete you should accept the offer to view the results.

  Within the error layer window you can select different error types on the left, different cells on the right and zoom to individual errors using the left and right arrows.

• While some errors may be rectified by post processing of the designs (e.g. dummy metal generation to overcome "density" problems), others will require you to modify your original magic design

Note that when you are learning how to use this DRC facility, it is best to check a magic design created with known errors. You can then track down the same errors using Assura DRC.

All Cadence documentation is available on-line.

For Virtuoso documentation use the help menu on the Virtuoso layout editor window:

  Help -> Virtuoso Documentation Library

For Assura documentation use the help button on the Run Assura DRC window:

  Assura -> Run DRC...

    Help

Full Design Rules for the TSMC 180nm process are also available via the Design Rule Documents web page.