L-Edit Place & Route

Preparation (Generation of Files)

Create Directory For Tanner Work


    mkdir -p ~/design/tanner/ex_control/place_route

Download the base C35B4 L-Edit library into this directory
c35b4.tdb
Generate a Structural SystemVerilog File
The following sequence of instructions will create a structural version of the controller for the example microprocessor design (You should also be able to generate a structural file based on your own control unit).
If all goes well you will see two example processor simulations. The first using the behavioural model of control.sv in the behavioural directory and the second using the newly synthesized gate level model of control.sv in the gate_level directory. Running this second simulation gives you confidence that the structural SystemVerilog file represents a circuit that will work after place and route.
```
    mkdir -p ~/design/synth/ex_control
    cd ~/design/synth/ex_control

    init_fcde_example behavioural

    ./simulate behavioural

    cp -pr behavioural gate_level
    rm gate_level/control.sv

    genus_custom -batch -pkg behavioural/opcodes.svh behavioural/control.sv gate_level/control.sv

    cp -p /opt/cad/bim/fcde/svfiles/no_state_view/system.fig gate_level/

    ./simulate -gate gate_level +define+no_state_view
```
Note that the new system.fig file from the no_state_view directory and the +define+no_state_view option for simulation are a "quick and dirty" way of ensuring that the simulation is not dependent on the names of the state signals inside the control module (since the these names change as a result of the synthesis process). A neater way to solve the problem is to edit gate_level/monitor.v and gate_level/system.fig so that they use the new signal names created by RTL Compiler.
For more details on the use of Genus synthesis see this lab.
Alternatively you can use Synopsys Design Compiler for synthesis in place of Cadence Genus. To do this, simply replace genus_custom in the command above with dc_custom (note that dc_custom may not work with all cell libraries - Synopsys Design Compiler is more fussy than Genus Synthesis).
Generate an EDIF Netlist File from the Structural SystemVerilog File
The vlog2edf script converts a structural verilog file containing a single module definition into an EDIF netlist file. The new file is then moved to the place and route directory.
```
    vlog2edf -fcde gate_level/control.sv control.edf

    mv control.edf ~/design/tanner/ex_control/place_route/
```
The -fcde option to vlog2edf removes any references to the global Clock and nReset signals from the EDIF file. This is essential since the Clock and nReset signals will not be routed explicitly by the L-Edit Place and Route tool. The removal of these signals will only work if the design is properly synchronous to the global "Clock" signal with the common "nReset" signal wired to all scanreg and scandtype cells.
Generate CIF file version of Cell Library
Note that L-Edit is even more fussy about labels than "check_magic_leaf_cell" so you may have to return to your cell library to correct errors and re-run this script several times.
```
    cd ~/design/fcde/magic/cell_lib

    create_cif_library

    mv cell_lib.cif ~/design/tanner/ex_control/place_route/
```

L-Edit Cell Library

Generate L-Edit version of Cell Library

Start L-Edit and open the C35B4 L-Edit library which you have copied

    ~/design/tanner/ex_control/place_route/c35b4.tdb

Note that since L-Edit is a windows tool, the actual directory location will be something like

    H:\design\tanner\ex_control\place_route

Now read in the CIF file that you have created:

  File -> Import Mask Data -> CIF...

    Import CIF
      From file:
        [ cell_lib.cif     ]
      Use setup file:
        [ c35b4.tdb        ]
    Import

This process should complete with no errors or warnings.

Now save the newly created L-Edit cell library:

  File -> Save As...

    Save As
      File name: [ cell_lib.tdb     ]
    Save

Place & Route

Create a Base L-Edit library file:

Create a new file:

  File -> New...

    New File
      File type:
        [ Layout           ]
      Copy TDB setup from file:
        [ c35b4.tdb        ]
    OK

Then save it with a new name:

  File -> Save As...

    Save As
      File name: [ control.tdb     ]
    Save

Place and Route task
Set up prior to place and route:
```
  Tools -> SPR -> Setup...

    SPR Setup
      Standard cell library file
        [ cell_lib.tdb     ]
      Netlist file
        [ control.edf      ]
    OK
```
The "Core Setup..." button on the SPR Setup dialogue allows you to customise the I/O signal placement for the place and route. There is no need to investigate this facility at this stage, but you will probably have to customise the I/O placement when you come to process your own control unit.
Run place and route:
```
  Tools -> SPR -> Place and Route...

    Standard Cell Place and Route
      Core configuration
        Constraint      [ Height    -]
        Number of rows          [ 2  ]
    Run
```
When prompted, agree to overwrite the empty I/O signal specification.
Modify Hierarchy
The new Core cell, contains subcells for the routing channels and the cell rows. Before going on, it is necessary to flatten these cells.
Select all items including the subcells:
```
  Edit -> Select All
```
Flatten the subcells:
```
  Draw -> Ungroup
```

Rename the Core cell:

  Cell -> Rename...

    Rename Cell Core
      Rename cell as: [ control           ]
    OK

Save the updated control.tdb library:
```
  File -> Save
```
Now export a CIF version:
```
  File -> Export Mask Data -> CIF...

    To File
      File name: [ control.cif     ]
      [ ] Export rectangular ports as centre points
    Export
```
At this stage you can ignore a warning about coordinate resolution although later you may find that this gives rise to minor errors in the final layout (these can be spotted by looking for design rule errors within magic).

Post Process

Create control.mag

Extract new CIF library to create magic files (extracted files are placed in a subdirectory named "magic_in")

    cd ~/design/tanner/ex_control/place_route/

    extract_cif_design control.cif

Convert internal labels to point labels

    cd ~/design/tanner/ex_control/place_route/magic_in

    labels2points control.mag

Check and Correct design rule violations
Open the control.mag magic design and use the magic commands :drc count and :drc find to identify design rule violations to be corrected (these normally come in the form of very small breaks in tracks caused by the different grids used by magic and L-Edit).
Even if you find no design rule violations you should still expand all the subcells and then save the design in order to remove timestamp mismatches.
Once you have corrected any design rule violations, you should check the design with "check_magic_cell". Although you may find that the origin is not at (0,0) and there may be missing GND! and Vdd! labels, there should be no other problems.
Edit the Magic Design to Include End Cells
L-Edit place and route does not understand end cells so you will have to delete the power and ground routing from control.mag and add "leftbuf" and "rightend" cells plus the appropriate wiring for Vdd!, GND!, Clock, nReset, Test, SDI and SDO.
Having added the end cells you will need to correct the origin.
Finishing Off
Ensure that you check the design again with "check_magic_cell". If there are no problems you can go on to extract and simulate the design. Note that even where the synthesis and the place and route processes complete successfully, the result of the post-layout simulation may not match the post-synthesis simulation which in turn may not match the pre-synthesis simulation. The difference in each case is in the delays simulated. None of the delays are accurate but you should ensure that all three simulations give the same results if you wish your design to be fabricated.

Iain McNally
18-12-2017