Xilinx FPGA Design

Your task is to synthesise the behavioural blocks that you wrote for the dice design exercise and then import them into Cadence as schematics so that a complete dice system can be implemented on a Xilinx FPGA.

Synthesis

The Cadence Ambit synthesis program is used to convert a behavioural verilog description into structural verilog.

• change to the directory containing the Cadence database for your random number generator design.

    sparc% cd ~/design/cadence/xilinx/hier
  

• create directories for behavioural and structural verilog files and copy the first behavioural file to be converted into the behavioural directory.

    sparc% mkdir behavioural structural
    sparc% cp <elsewhere>/<cell>.v behavioural/<cell>.v
  

• invoke the NaviGates user interface to Ambit synthesis

    sparc% synth_xilinx
  

• read in the behavioural verilog file

  open the Read HDL Files files dialog

    File -> Read HDL...
  

  • select the behavioural sub-directory
  • double clicking on the <cell>.v file will bring it up in the Selected Files: field
  • select the file within this field and then press the Read & Build button

• correct any errors and check any warnings

  During the Read & Build operation the verilog file is parsed for syntax errors and then synthesized using a generic library - either of these operations may give rise to errors.

  (although a verilog file which has been simulated with Verilog XL should not should not give parsing errors you may get warnings or errors relating to unsynthesizable constructs)

  Rather than editing the verilog file using Nedit and repeating the Read & Build step, it is often preferable to use the editor functions provided within NaviGates. Simply trebble click on the error message to open an editor window with the offending command hilighted.

  Having corrected any error the original file is updated and the new file parsed using the Save & Parse button.

  With no parsing errors the design may be synthesized using the generic library by selecting Tools -> Build Generic

  Failure at this stage is usually due to unsynthesizable verilog. In fact the Ambit synthesis system supports only a subset of the parts of the Verilog HDL which are considered synthesizable (e.g. it doesn't support the modulus operator; %).

  You may need to consult the Ambit documentation for more details. In particular the Verilog Modelling Style chapter from the user's guide gives details of suggested style while the Verilog Support chapter gives details of supported and unsupported constructs.

• check the ouput for latches etc.

  The Build Generic step performs useful analysis on the design and returns results in the bottom pane of the NaviGates window.

  Analysis is performed on various aspects including the presence of sequential elements (latches and flip-flops) in the synthesized design. In general the presence of a sequential element of type Latch rather than D_FF in your final design indicates a problem with your behavioural model. Possibly a latch has been inferred within a block which was intended to represent combinational logic. This will happen where the guidelines on using Procedural Blocks as Combinational Logic have been breached. See Hardware Modelling documentation for more detail.

  Other useful information given includes the identification of incomplete case statements which may in themselves give rise to inferred latches within combinational blocks.

• map to Xilinx library and optimize for area

    Tools -> Optimize...
  
      Optimize Options
        priority
          [x] area
      Optimize
  

  again, a failure here is likely to indicate problems with your behavioural model.

• write out the structural verilog file

    File -> Write HDL...
  
      Writing Module <module name>
        Files:        [ <cell>.v       ]
        Directories:  [ structural     ]
      OK
  

Verilog Import

If the synthesis has been succesful the verilog import into Cadence should be straight forward.

• ensure that you are in the correct directory

    sparc% cd ~/design/cadence/xilinx/hier
  

• run the import script

    sparc% ihdl_xilinx structural/<cell>.v
  

  by default the new schematics will be created in a library called dest_sch_lib, although this can be changed by using the -d <lib> option to the ihdl_xilinx command.

At this stage you can repeat the Synthesis and Import procedures for any remaining behavioural cells.

Cadence Modifications

Having created new cells you will need to incorporate them into your existing Cadence design.

• start Cadence for Xilinx libraries

    sparc% cds_xilinx
  

• use the library manager for library, cell and cellview manipulation

    Tools -> Library Manager...
  

  within the library browser the left hand mouse button is used for navigating around the library structure while the middle mouse button provides access to the commands used to manipulate the libraries, cells and cellviews.

  • browse through the libraries to check that schematics are generated as you expected - open the corresponding schematics in read only mode to see what has been created.

  • copy your existing toplevel cell to avoid loss of work

  • edit the new top level cell to include the symbols for the newly synthesized cells.

Completion

• use simulation to confirm the success of the synthesis operation

• finish off by generating a new bitstream file and downloading it to the FPGA.

All Cadence documentation is available on-line via openbook. Type the following at the unix command prompt in order to invoke openbook:

openbook IC

Ambit documentation is also available on-line as HTML files:

• Ambit Bookshelf

  The following chapters should be of particular interest for this exercise.

  • Verilog Support
  • Verilog Modelling Style