Xilinx FPGA Design

- using Cadence Schematic Capture

Task

Your initial task is to implement a random number generator based on the one previously used for the dice design exercise.

Two cells will be designed; the first will include the gates required to complete the random number generator function while the second will be a top level cell including the I/O buffers required by the FPGA.

This hierarchical approach helps to introduce you to the Cadence tools and allows easy expansion to produce a full implementation of your dice design.

You should verify your design using verilog simulation and download it onto a Xilinx FPGA for final testing.

Documentation

You are not required to write a formal report on this exercise, but you should ensure that you keep a good record of the work done in your laboratory log book. As mentioned for an earlier exercise, log books do not contain loose paper; handouts and printouts are attached permanently using staples or glue, anything which falls out when a log book is shaken is not considered for marking.

Procedure

Library Manipulation

change to a new directory which will contain the cadence database files

  sparc% mkdir -p ~/design/cadence/xilinx/hier
  sparc% cd ~/design/cadence/xilinx/hier

start Cadence for Xilinx libraries
```
  sparc% cds_xilinx
```

open a new library

use the Command Interpreter Window menus then fill in the form

  File -> New -> Library...

    New Library
      Library
        Name            [ <my_lib>                  ]
      Technology File
        [x] Don't need a techfile
    OK

Schematic Cell Design

open a new design for edit

  File -> New -> Cellview...

    Create New File
      Library Name      [ <my_lib> - ]
      Cell Name         [ <my_cell>                 ]
      View Name         [ schematic                 ]
    OK

add instances as required:

note that each of the following commands can be invoked in at least four ways, you should experiment with the different methods to decide which suits you best.
- components
```
  Add -> Instance ...

    Add Instance
      Library           [ xc4000                    ]
      Cell              [ <xilinx_cell>             ]
      View              [ symbol                    ]
```
  - unless you know the name of the cell that you're looking for use the Browse button.
  - in this exercise all leaf cells must come from the xc4000 library since our target FPGA is an XC4010E-PC84 from the Xilinx 4000 series.
  - cells that will be useful include xvcc, xgnd (used to tie unused inputs) and fdc (a D-type flip-flop with active high clear).
  - when you get to designing higher level cells you will have to add components from your own library <my_lib> in order to achieve the required hierarchical design.
- add wires:
```
  Add -> Wire (narrow)
```
- add pins:
```
  Add -> Pin ...

    Add Pin
      Pin Names         [ <my_pin>                  ]
      Direction           <input/output>
```
  note that bus signals in cadence are specified using angle brackets - e.g. count<3:0>
check and save cellview
```
  Design -> Check and Save
```
create symbol for use in higher levels
```
  Design -> Create Cellview -> From Cellview ...
```
- defaults should create an appropriate symbol from your schematic
- close the resulting symbol editor window

Simulation

initialize the environment for a Verilog simulation (from the schematic editor window)
```
  Tools -> Simulation -> Verilog-XL
```
- defaults should be fine to open a new Verilog-XL control window

create a stimulus file for the simulation

  Stimulus -> Verilog

when prompted agree to create a new stimulus template file

    Stimulus Options

      Mode
        [x] Copy
      Copy From:
        File Name         [ testfixture.verilog       ]
      Copy To:
        File Name         [ <my_cell>_stim.v          ]
      [x] Make Curent Test Fixture

    OK

Edit the new stimulus file

  Stimulus -> Verilog

    Stimulus Options

      Mode
        [x] Edit
      File Name           [ <my_cell>_stim.v          ]
      [x] Make Curent Test Fixture
      [x] Check Verilog Syntax

    OK

add stimulus information as required
- add time delays and appropriate inputs
- terminate with $finish;

simulate

start simulation
```
  Simulation -> Start Interactive
```
continue until $finish;
```
  Simulation -> Continue
```

view output
- open waveform window (from Verilog-XL control window)
```
  Debug -> Utilities -> View Waveforms
```
- Find required signals using SignalScan Design Browser and copy and paste them to the waveform window. This can be done by selecting the GetDeepAll button followed by the AddToWave button after opening the Design Browser using the DesBrows:1 button. Select full zoom in X direction to see the results: ZmOutXfull.
- To probe additional signals, type $shm_probe("AC"); after selecting Start Interactive. You will probably have to be more selective when choosing signals from the Design Browser window to ensure you see only the signals you want.

Further Cells

for subsequent cells you should repeat the described schematic cell design and simulation steps

Top Level Cell

for the cell at the top of the hierarchy you must include details of the FPGA pinout.

include io buffer cells ibuf and obuf

for each such buffer cell you should specify the pin location

  Edit -> Properties -> Objects...

select one of the io buffer cells

  Edit Object Properties :- Add

    Add Property
      Name              [ LOC                       ]
      Value             [ P<n>                      ]
    OK

change display status for the new property to both and then Apply the changes you have made.

the result should be similar to that shown below:
repeat the process for the remaining io pins.

Since the hardware has already been built, you are restricted in your choice of pinout. Although other pins are connected, the following should suffice for this exercise:

system inputs
clock	P13
_reset	P56
LEDs for dice display (active high)
TL	P84
ML	P6
BL	P8
MC	P4
TR	P80
MR	P78
BR	P82
7-segment display (active low)
a	P49
b	P48
c	P47
d	P46
e	P45
f	P50
g	P51
dp	P41
general purpose inputs
SW5-1	P27
SW5-0	P28
general purpose outputs(active low)
O0	P60
O1	P59
O2	P58
O3	P57
O4	P66
O5	P65
O6	P62
O7	P61

Design Translation

Having designed and simulated the top level cell you will need to create a Xilinx bitstream file suitable for downloading into the FPGA.

From a unix command window ensure that you are in the correct design directory.
```
  sparc% cd ~/design/cadence/xilinx/hier
```
Now run the following script:
```
  sparc% alliance_script <my_lib> <top_cell>
```
this command will:
- Create an alliance/my_lib/top_cell directory in which the Xilinx tools will be run
- Create a top_cell.xnf Xilinx netlist file
- Create a top_cell.bit Xilinx bitstream file
If errors are reported consult the appropriate log files in the alliance/my_lib/top_cell directory for details.
Alternatively you might like to try re-running the script in interactive mode:
```
  sparc% alliance_script -i <my_lib> <top_cell>
```

Programming the FPGA

One of the workstations should have the XC4000 Design Demonstration Board connected to it via an Xchecker cable attached to serial port B.

open a remote window on the appropriate workstation (where remote login is not permitted you will have to login directly to this workstation).

change to the alliance/my_lib/top_cell directory.

  xihost% cd ~/design/cadence/xilinx/hier/alliance/<my_lib>/<top_cell>

run the download software.
```
  xihost% hwdebugr <top_cell>.bit
```

If everything has gone exceptionally well you should find that the demonstration board performs the function you have designed.

Example Design

The Example design shown below illustrates many features that you will need to incorporate in your own designs.

The following figure shows a design for a 3 bit counter.

The fdc D-type has no nq output, hence an inverter is required for the generation of Count<0>.

The inverter on the nReset input to allow for the active high clear on the D-types.

The wire labels for Count<0>...Count<2> are used to make connection to the Count<2:0> ouput pin. This join by label technique is often used to reduce the clutter on schematic diagrams.
The following figure shows the corresponding top level cell.

The count symbol is used to reference the count schematic above.

Each ibuf and obuf has a LOC value to map it to the appropriate FPGA pin.

Inverters are used on the outputs to provide the required active low signals.

Dice LEDs & Seven Segment Display

Additional Documentation

All Cadence documentation is available on-line via openbook. Type the following at the unix command prompt in order to invoke openbook:

openbook IC

Additionally Xilinx documentation for FPGAs and the Alliance software is available as on-line help or from the Xilinx web site.

Iain McNally

13-12-2000