Cadence Place & Route using AMS 0.35µm Libraries

Prerequisites

This design flow expects that you are working in a design directory (e.g. ~/design/ams/ams_demo) with a number of sub-directories containing files created during the preceding synthesis stage:

gate_level
This directory contains a gate-level verilog netlist <topcell>.v (e.g. cpu.v) and an associated delay file <topcell>.sdf (e.g. cpu.sdf)
padring
This directory contains a pad ring specification file <topcell>.io (e.g. cpu.io)
constraints
This directory contains a design constraints file design.sdc (e.g. design.sdc)

Preparation

Note - if you read the whole of the preparation section before typing any commands you may save yourself some time and some typing.

Within your working directory (e.g. ~/design/ams/ams_demo), create a new sub-directory for the place and route files and change to the new directory:

    mkdir place_route
    cd place_route

Now run the ams_edis script with appropriate options to specify a 4-metal 0.35µm process running at 3.3 volts with core cells from the CORELIB library and pad cells from the IOLIB library:

    ams_edis -tech c35 \
      -vn <topcell>.v -vt <topcell> \
      -metlay thin4M \
      -corelib CORELIB \
      -corevolt _3.3V \
      -corevolt_wc _3.3V \
      -corevolt_bc _3.3V \
      -iolib IOLIB \
      -iovolt _3.3V \
      -iovolt_wc _3.3V \
      -iovolt_bc _3.3V \
      -ediver EDI13.1ISR4

Following this, you will need to add symbolic links for the gate-level netlist and the constraints file mentioned above to ensure that the place and route software can find them:

    ln -s ../../gate_level/<topcell>.v VERILOG/<topcell>.v
    ln -s ../../constraints/design.sdc CONSTRAINTS/<topcell>_func.sdc
    ln -s ../../constraints/design.sdc CONSTRAINTS/<topcell>_test.sdc

Note that the AMS scripts expect separate constraints files for functional mode (<topcell>_func.sdc) and test mode (<topcell>_test.sdc). This might allow us to specify tight timing constraints for the functional mode and looser constraints (e.g. a slower clock speed) for the test mode. For this walkthrogh we have generated only one set of timing constraints, so we link both of the expected files to the single constraints file (design.sdc).

If if the source files are as specified in the prerequisites section above and you do not want to change any of the options to the ams_edis script, you can use the following sequence of commands in place of those above:

    prepare_edi <topcell> place_route
    cd place_route

Import the design

Within your new place and route directory (e.g. ~/design/ams/ams_demo/place_route), use the "encounter" command to start the place and route tool:

    encounter

You should see a new GUI window where you will later see the chip layout take shape. For now you should look at the terminal window where you should find the encounter prompt: "encounter 1>". Here you should type the following sequence of commands to import the design:

Set a TCL variable for I/O definition file that we will need later
```
    set io_filename "../padring/<topcell>.io"
```
Initialise the database (load in the design)
```
    amsDbSetup
```

Setup timing

    amsSetMMMC
    amsSetAnalysisView minmax {func test}

Place the pad cells (including corners and power) and then snap them to the grid
```
    loadIoFile $io_filename
    amsUserGrid
```
View design in GUI
```
    fit
```

If all goes well, you will see your pre-defined padring in the GUI window following the fit command.

Note that commands in the list above which start with "ams" are AMS specific commands. These commands are defined in the "amsSetup.tcl" file which is a TCL script created by the "ams_edis" script. This "amsSetup.tcl" script invokes Cadence commands; later you will write your own TCL script to invoke the commands needed to place and route your design.

Add power rings and power routing

The instructions below will add two 20µm power rings between the core and the pads. The power rings use metal 3 horizontally and metal 4 vertically and are spaced 2µm apart (any track over 10µm in width is treated as a wide track which requires greater than usual spacing to other design elements — 2µm is the minimum spacing for wide metal tracks on the thick metal 4 layer).

Once the power rings have been added we can perform the power routing for the connections to the pad cells and the core rows which will later hold the standard cells.

Create some space for the power rings — 60µm spacing is plenty for 2x 20µm power rings
```
    floorPlan -r 1 0.7 60 60 60 60
```
as well as the 60µm core to pad ring spacing, the -r options above specify a core aspect ratio of 1 (i.e. 1:1 or square) and row density of 0.7 (i.e. 70% utilisation).
Specify the connectivity of the global power nets
```
    amsGlobalConnect both
```
Specify the connectivity of the global power nets to core power pads.
```
    globalNetConnect gnd! -type pgpin -pin A -inst CORE_GND_* -module {}
    globalNetConnect vdd! -type pgpin -pin A -inst CORE_VDD_* -module {}
```
note that these commands assume that the instance names for the core power pads in the gate-level verilog netlist have names beginning "CORE_GND_" and "CORE_VDD_".

Add the gnd! and vdd! power rings in the centre of the space around the core using metal 3 and metal 4 with a width of 20µm and a spacing of 2µm

    addRing \
      -type core_rings \
      -nets {gnd! vdd!} \
      -center 1 \
      -layer {bottom MET3 top MET3 right MET4 left MET4} \
      -width 20 -spacing 2

Add power and ground routing (special route)

    sroute \
      -connect { blockPin padPin padRing corePin floatingStripe } \
      -layerChangeRange { MET1 MET4 } \
      -blockPinTarget { nearestTarget } \
      -padPinPortConnect { allPort oneGeom } \
      -padPinTarget { nearestTarget } \
      -corePinTarget { firstAfterRowEnd } \
      -floatingStripeTarget { blockring padring ring stripe ringpin blockpin followpin } \
      -allowJogging 1 \
      -crossoverViaLayerRange { MET1 MET4 } \
      -nets { vdd! gnd! } \
      -allowLayerChange 1 \
      -blockPin useLef \
      -targetViaLayerRange { MET1 MET4 }

At this stage you should save your work.

    saveDesign floorplan.enc

The "floorplan.enc" file specified in the command does not contain the design data itself but it does contain information required to restore the saved design later (the design data itself is stored in a Cadence library directory named "FEOADesignlib" with a cell name "<topcell>" and a view name "floorplan").

If you need to recover this version of the design later, you can start encounter with the following options: encounter -init floorplan.enc -win

Placement

The next stage is to place the standard cells in the core.

Change from flooplan view to placement view so that we can see the cells
```
    setDrawView place
```
Place standard cells in rows and cap cells at the end of each row.
```
    placeDesign
    amsAddEndCaps
```

Add Tiehi/Tielo cells

    setTieHiLoMode -cell {TIE1 TIE0} -maxFanout 10
    addTieHiLo

Save intermediate design
```
    saveDesign placed.enc
```

Two things to note here are that the "placeDesign" command seems to have added wiring as well as cells and the row utilisation (at least for small designs) is much less than the 70% specified during the "floorPlan" command above. The wiring that you see is as a result of a trial routing stage and will later be replaced by the actual routing. The row utilisation is less than 70% for small designs because the design is pad limited rather than core limited (i.e. the size of the design is primarily a function of the number of pads rather than a function of the number of gates in the design).

Pre-CTS Optimisation

    # Pre-CTS Optimisation

    setOptMode -fixCap true -fixTran true -fixFanoutLoad false
    optDesign -preCTS
    optDesign -preCTS -drv

Clock Tree Synthesis


    # Clock Tree Synthesis (c.f. Michael Nydegger)
    # for small designs with a clock buffering pad there may be few if any clock buffers in the tree


    setCTSMode -engine ck

    setCTSMode -traceDPinAsLeaf true -traceIOPinAsLeaf true

    createClockTreeSpec \
      -bufferList {CLKBU2 CLKBU4 CLKBU6 CLKBU8 CLKBU12 CLKBU15 CLKIN0 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN6 CLKIN8 CLKIN10 CLKIN12 CLKIN15} \
      -routeClkNet -output CONSTRAINTS/clock.clk


    # Michael Nydegger does this but I don't think we need to -
    # system "sed -i 's/^AutoCTSRootPin.*$/AutoCTSRootPin PAD_Clock\\/Y/' CONSTRAINTS/clock.clk"

    specifyClockTree -clkfile CONSTRAINTS/clock.clk

    ckSynthesis

Save intermediate design
```
    saveDesign inc_clock_tree.enc
```

Post-CTS Optimisation



    # Post-CTS - update constraints

    set_interactive_constraint_modes {func test}

    # replace predicted latency and transition with actual values through clock tree
    set_propagated_clock [all_clocks]

    # set jitter to 0.5 ns (clock skew is no longer important)

    set_clock_uncertainty 0.5 [get_clocks master_clock]

    set_analysis_view -setup {func_max func_typ func_min} -hold {func_max func_typ func_min}



    # Post-CTS Optimisation

    optDesign -postCTS -hold
    optDesign -postCTS -drv

Routing and Final Optimisation


    # Add filler cells before routing

    amsFillperi
    amsFillcore

    # route with nanoRoute

    routeDesign -globalDetail

    # Post-route optimisation

    setDelayCalMode -engine default -siAware true
    setAnalysisMode -analysisType onChipVariation

    optDesign -postRoute -hold
    optDesign -postRoute
    optDesign -postRoute -drv


    # Save final design

    saveDesign routed.enc

Scripting the design flow

Iain McNally
2-9-2016