ARM System on Chip (Introductory Altera FPGA version)

This walkthough aims to introduce you to a simple ARM SoC and the hardware/software design flow.

This walkthough is one of a number which help to illustrate the principles of ARM SoC design:

ASIC version	Introductory ASIC version
FPGA version	Introductory FPGA version
Altera FPGA version	Introductory Altera FPGA version

While the first three versions include examples of custom interface hardware typical of a System-on-Chip design, the "Introductory" version(s) include non-specific input and output ports in the manner of a microcontroller system. While the use of custom interface hardware is likely to yield better results (if it doesn't yield better results you will probably be better off using a microcontroller rather than an SoC), the use of non-specific input and output ports can aid understanding and can offer a starting point for the design of custom interface hardware.

A very simple ARM System on Chip has been designed:

0. RAM
   16K bytes for program and data memory (including stack)

1. Input Port
   Occupying one 32-bit memory location

2. Output Port
   Occupying one 32-bit memory location

Memory Map

• The memory map is sparsely populated with the unused areas being filled with secondary images of the real slave devices:
  

  The secondary images are an artefact of the partial address decoding which only uses the top 4 address bits (HADDR[31:28]) in order to decide which slave is being accessed.

Files

In order to build the ARM SoC, we need SystemVerilog files to model the hardware plus 'C' program files and other support files to build the software. Further files are required to support simulation:

• Hardware
  • arm_soc.sv
    • CORTEXM0DS.sv
    • ahb_interconnect.sv
    • ahb_ram.sv
    • ahb_input_port.sv
    • ahb_output_port.sv

• Software
  • C Program Code
    • main.c
    • vectors_designstart.c
    • crt.c
  • Support files
    • compile_and_link
    • makefile
    • designstart.ld

• Simulation
  • arm_soc_stim.sv
  • arm_soc.tcl
  • simulate

Preparation

• Create a new directory for the lab (e.g. ~/design/system_on_chip/example_altera_introductory) and change to the new directory:

      mkdir -p ~/design/system_on_chip/example_altera_introductory 
      cd ~/design/system_on_chip/example_altera_introductory

• Copy the design files (not including the Cortex-M0):

      init_soc_altera_introductory_example -here
  

• Download the obfuscated Cortex-M0 file and place it in the behavioural subdirectory:
  • cortexm0ds_logic.sv

Compile C Program

• In the software sub-directory, the compile_and_link script, the makefile and the designstart.ld linker script are used to compile the three C language files main.c, vectors_designstart.c and crt.c.

  Running the compile_and_link script:

      cd software
      ./compile_and_link
  

  should create a Verilog hex format file named "code.hex" which can be used in simulation and synthesis.

• Open the "code.hex" file in a text editor to check that it has been created.

Simulate ARM SoC

• In the main directory (~/design/system_on_chip/example), a simulate script exists to simplify the task of running the simulation:

      cd ..
      ./simulate &
  

  (The xmverilog command to run the simulation is:

      xmverilog +gui +access+r \
                +tcl+testbench/arm_soc.tcl \
                -y behavioural +libext+.sv \
                +define+prog_file=software/code.hex \
                +define+prog_file_vmem=software/code.vmem \
                testbench/arm_soc_stim.sv
  

  but it's easier to use the simulate script)

• Consult the HADDR and HSEL_... signals in the waveform window and satisfy yourself that the correct active HSEL_... signal is being selected based on any particular address value. (Identify at least one address for each of the HSEL_... signals and confirm that it is in the correct range)

• Look at the Console output and the main.c program. Can you explain the sequence of "oPort" values that you see in simulator console?

Synthesis

In order to synthesise the system onto an FPGA development board you will need a top level "wrapper" file and a matching constraints file:

Create a custom interface

The key to system-on-chip design is the creation of custom interface hardware.

A modified ARM System on Chip including a simple custom interface is to be designed:

1. Create the custom interface

   The file name for the interface should be ahb_custom_interface.sv and it should be placed in the existing behavioural/ directory.

   A template for the custom interface can be found here: ahb_custom_interface.sv

   You will need to take the template and fill in the code where it is missing. You can base the code that you enter on the code from the output port module: ahb_output_port.sv. Since the custom interface supports more than one address, you will need to add code to generate a word_address signal during the address phase. An example of this sort of code can be found in this example module: ahb_switches.sv

2. Create a new SoC top-level module

   The file name for the top-level module should be arm_soc_custom.sv and it should be placed in the existing behavioural/ directory.

   You can base the new module on the existing SoC module code: arm_soc.sv.

   Changes that you should make are:

   • The module name needs to be changed to arm_soc_custom
   • The existing oPort signal should be replaced in the port list with the four new ports: oA, oB, oC and oD.
   • The existing ahb_output_port module instance should be replaced with a module instance for the new interface, ahb_custom_interface.

   Note that there is no need to change the interconnect module (ahb_interconnect.sv) because the new interface occupies the same area of the memory map (0x5000000-0xFFFFFFFF) as was previously occupied by the output port.

3. Simulate the complete design

   The testbench/ directory already includes a arm_soc_custom_stim.sv testbench file to test the new system. The command to use is:

       ./simulate testbench/arm_soc_custom_stim.sv &
   

   If all goes well, the behaviour of the new system will match that of the old one since the the 'C' program is unchanged. The only difference is that the the output values are being written via oA rather than oPort.

4. Modify the 'C' program

   Now modify the 'C' program to access the other registers in the custom interface.

   Changes that you should make are:

   • Add the following 'C' code to enable the registers within the custom interface to be accessed:

     // Define the raw base address value for the custom interface
     
     #define AHB_CUSTOM_BASE                         0x50000000
     
     // Define a pointer with correct type for access to 32-bit registers
     //
     // The the four registers in the interface can then be accessed as:
     //    CUSTOM_REGS[0]
     //    CUSTOM_REGS[1]
     //    CUSTOM_REGS[2]
     //    CUSTOM_REGS[3]
     
     volatile uint32_t* CUSTOM_REGS = (volatile uint32_t*) AHB_CUSTOM_BASE;
     

   • Add 'C' code at the beginning of the main function to set oB equal to 42.

   • Add 'C' code within the while(1){...} loop to set oC equal to read_switches().

   • Add 'C' code within the while(1){...} loop to set oD equal to oC + 1.

   After each change you should recompile the code then re-run the simulation and check that the new behaviour is as you expect.

Having completed this lab walkthrough, you should have a basic understanding of SoC design including an ability to build a simple custom interface and write a 'C' program to access the interface.

At this stage you can experiment with other changes to the system but you should try to make only small changes between simulations to increase the chances of being able to debug the system. For example, if your FPGA includes a seven-segment display, can you add a custom interface which includes a seven-segment encoder?