Naming Conventions for CAD

Name Problems

When completing a large electronic design such as a full-custom integrated circuit, it is likely that many CAD tools will be involved. Each tool will have restrictions on naming. Even when all tools are provided by the same vendor it is likely that different tools will have different naming restrictions. In order to get a design through all design stages it is best to take a highest common factor approach; what sort of name is acceptable to all of the tools.

The simplest problems are with case sensitivity. Some tools are case sensitive while others are not (e.g. Verilog HDL is case sensitive while VHDL is case insensitive). Where multiple tools are used the only way to avoid ambiguity is to be case consistent, thus we should never use the names Signal1 and signal1 in the same design since we will not be sure whether they will be connected.

Name problems may occur for each of the following items:

• directory names -
• file names -
• cell names -
• instance names -
• signal names -

Guidelines

A few simple guidelines will help you to avoid most problems:

• Always be consistent with case.

• All names should start with a letter.

  A cell name, 3nand, may be interpreted as a badly formed number by some tools.

• Do not use spaces.

  Using the Microsoft Program Files directory for installation causes certain CAD tools to fail. Note that the use of capital letters may make names readable without the problems of spaces - e.g. MyCadDirectory or XBusEnable

• Avoid other special characters.

  Avoid characters other than a-z A-Z 0-9. The possible exception to this rule is the underscore character _ which is acceptable to most tools.

• Avoid over long names.

  There is no hard and fast rule here but if you want to keep safe then names of 8 characters or less are unlikely to cause a problem. This rule conflicts with the requirement to use meaningful names for clarity so a working maximum of around 12 characters may be better.

• Beware of reserved names.

  This one is difficult to predict unless you know the reserved names in advance. Verilog uses nand, nor, and, or and not as reserved words.