Hierarchy

• Complexity Control

  Hierarchy is used to simplify the design of complex systems. The strategy is one of Divide and Conquer. A module is divided into sub-modules which in turn are sub-divided until the complexity of the modules becomes manageable.

  Significant benefits acrue where modules may be re-used within a system design. In this case we create a single design for this module but we use several instances of this design in different parts of the system.

• Modularity

  Sub-modules must have well-defined functions and interfaces. Where modules are well-formed, the interactions with other modules are easy to characterize.

  In the case of layout, the interface is defined by the ports of the sub-modules which must be at specified locations and using specified conductors. In the following example, inputs In1 and In2 are at specified locations on the Metal1 layer while the output, Out, is located as specified on the Metal2 layer:

  

• Locality

  By defining well-characterized interfaces for a module, we are stating that any other internal detail is unimportant to any parent module. In this way, we hide information in an attempt to reduce the apparent complexity of a module.

  A side effect of this complexity hiding is that a sub-module may be changed at any time without disturbing the overall design provided that the changed sub-module continues to support the same interface.

  For locality to work, we must impose restrictions on the use of a sub-module. In the case of layout, we must avoid making unwanted connections to elements in the sub-module and we must avoid design rule violations caused by the proximity of external elements to internal elements.

  To support these we come up with two general rules for good hierarchical design using locality:

  1. Connections to Sub-Cells

     When making connections to any sub-module connections may only be made at defined ports.

  2. Keep Out Areas

     In addition, external wiring may not encroach on certain explicit or implicit keep out areas, over or around the cell.

  Black Box or Abstract View

  The following figure shows the ports defined earlier together with explicit Metal1 and Metal2 keep out areas which ensure that no unwanted interaction takes place. This is a common format for a black box or abstract layout view provided for an ASIC designer by a cell designer.

  

  Note that the keep out areas overlap the cell boundary in order to ensure that external Metal1 and Metal2 cannot be placed close enough to the cell to violate spacing rules.

  Below are two abstract layouts for NAND gates, illustrating some more complex features:

  • NAND gate for 2 metal process
    

    Here we see I/O at top and bottom and power connections at either side. A gap in the Metal2 keep out between B and Y indicates that the cell may be over-routed with Metal2 along this path.

  • NAND gate for 3 metal process
    

    Here we see central I/O and power connections along the top and along the bottom. There is no Metal2 keep out indicating that we can route Metal2 anywhere over the cell. There is no Metal1 keep out above the V_DD rail or below the GND rail indicating that we can butt cells together in two dimensions:

    

    Note here that the second row of cells is upside down so that the GND rails match.

• Regularity

  Regularity controls the manner in which sub-modules are chosen. The strategy is to avoid replacing a complex system design with a complexity of sub-modules. The designer attempts to divide the hierarchy into a set of similar blocks.

  In the case of layout, the leaf modules (i.e. those that contain no sub-modules) will often be standard logic functions such as NAND/NOR/XOR built to a common specification.

  The common specification may include features such as:

  • Cell Height
  • Location, Size and Conductor Type of Power Rails
  • Location, Size and Conductor Type Size of I/O

  Example Common Specification:

  • Cells 6.0um high
  • V_DD rail in Metal1, width 0.8um and centered 5.0um from the bottom of the cell
  • GND rail in Metal1, width 0.8um and centered 1.0um from the bottom of the cell
  • N-Well between 3.0um and 5.5um from the bottom of the cell
  

  Here it can be seen that these common rules allow for the butting of leaf cells such that V_DD and GND rails and also the N-Well connects.

  1/2 Design Rule Spacing

  To ensure that butting is always possible, we must also consider the keep out areas for a cell. The simplest common specification for the keep out area is as follows:

  • The keep out area for each layer should extend for one half of one design rule distance beyond the edge of the cell.

  • Internal elements within the cell should be at least one half of one design rule distance inside the cell boundary.

  The following figure shows keep out areas for Metal1 and Metal2 for a part of a cell, together with internal elements sufficiently inside the cell boundary.

  Note: Remember that diffusion spacing rules are likely to be greater than metal spacing rules. All internal elements on all layers must be at least one half of one design rule distance inside the cell boundary.

Magic

Magic will not enforce hierarchy rules. If you don't obey hierarchy rules, a few things may not work but in general you'll just get a messy, difficult to debug, difficult to explain system.

To help you produce good hierarchical designs it is strongly suggested that you follow the conventions outlined below:

• Ports

  By convention, ports in magic are indicated by non-point labels on a particular layer.

  Point labels may be used to label internal nodes that are not intended as ports.

  In three input NAND gate below, the ports (A, B, C, Y, Vdd! and GND!) are indicated by line labels along the edges of the cell while internal nodes (n1 and n2) are indicated by point labels:

  

  The magic router also supports the labelling style shown below which uses rectangles for port labels:

  

  Although supported by magic, this style is not supported by Tanner L-Edit. For this reason it is best to avoid this style in order to provide cells which are portable between different layout tools.

• Keep Out Areas

  Keep out masks are essential where a cell designer supplies only abstract views of the leaf cells to an ASIC designer.

  For most small full custom projects, abstracts are not required since the full details of the leaf cells are available.

  Your work with magic will not require explicit keep out masks, but you will be required to observe implied keep out areas as appropriate.

  Where three metal layers are not in use, the following guidelines should be followed:

  1. Cells may butt but should not overlap.

  2. Wiring should be at least 1/2 a design rule from a sub-cell except where a connection to a port is made.

  3. Internal elements which might cause design rule errors should be at least 1/2 a design rule from the cell boundary.

  4. Ports should be placed only along the edges of cells.

  5. Wiring should not normally overlap a sub-cell.

• Design Rules For Diffusions

  Since magic autogenerates the PIMPLANT mask around p-type diffusions, you must consider PIMPLANT minimum spacing rules when calculating the 1/2 design rule spacing for diffusions.

  Taking the "cmos05" technology as an example, the PIMPLANT mask will overlap each diffusion region by 0.5µm and the minimum spacing for the PIMPLANT mask is 0.8µm. Thus two diffusions must be separated by 0.5µm + 0.8µm + 0.5µm = 1.8µm. The figure below shows the normal magic layers overlaid with the autogenerated PIMPLANT mask:

  

  In fact magic can cope with diffusions closer than 1.8µm by drawing extra PIMPLANT to join them together. Unfortunately it's ability to cope depends on the alignment of the diffusions. In the figure below magic satisfactorily joins one pair of diffusions while the other causes a design rule error:

  

  1/2 Design Rule Distance For "cmos05" Diffusions

  Thus in order to guarantee no design rule errors when cells are placed next to each other, each diffusion/ diffusion_contact/ tap should be at least 0.9µm (i.e. 1.8µm/2) from the left or right edge of the cell.

  Explicit P-Implant

  One approach to reducing errors caused by autogenerated PIMPLANT involves drawing explicit PIMPLANT areas. To add explicit PIMPLANT, use the magic command :paint pimplant.

  The explicit PIMPLANT can be drawn oversize to ensure that there are no problems with the autogeneration:

  

  Alternatively patches of explicit PIMPLANT can be drawn to augment the autogenerated PIMPLANT to overcome specific design rule errors:

  

  Note that it is not possible to get rid of all PIMPLANT errors by adding explicit PIMPLANT. In the figure below, the autogenerated PIMPLANT generates errors since it narrows to a width of zero between the two p-type transistors. Unfortunately the proximity of the two n-well taps prevents the addition of any explicit PIMPLANT to remove the error:

  

  1/2 Design Rule Distance For "cmos05" Diffusions (Alternative Version)

  1. If the cells in the library each contain only one row of PMOS and one row of NMOS transistors, there is no misalignment of diffusions so the autogenerated PIMPLANT will not give rise to errors where cells meet. In this case we can use a less stringent rule that each diffusion/ diffusion_contact/ tap should be at least 0.5µm from the left or right edge of the cell.

  2. If all taps lie along the power rails at the top and bottom of the cells, we can use explicit PIMPLANT to ensure that there are no errors where cells meet. Thus again we can use the rule that each diffusion/ diffusion_contact/ tap should be at least 0.5µm from the left or right edge of the cell.

  3. Where transistors are interspersed with taps, we must leave room for explicit PIMPLANT at the join between cells. A good rule to use is to ensure that taps must be 1.3µm from the right edge of a cell to leave room for a 0.8µm stripe of PIMPLANT. Other than this 0.5µm spacings can be used:

     

Further Reading

• CMOS VLSI Design, Weste and Harris, 3rd Edition, pp 485-498

  The topics of hierarchy, regularity, modularity, and locality in the wider context of VLSI design (not just layout) are covered well in this text.